參數(shù)資料
型號: M34524MC-XXXFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64
文件頁數(shù): 115/163頁
文件大?。?/td> 1235K
代理商: M34524MC-XXXFP
Rev.2.00
Jul 27, 2004
page 53 of 159
REJ03B0091-0200Z
4524 Group
Fig. 39 Serial I/O register state when transfer
(1) Serial I/O register SI
Serial I/O register SI is the 8-bit data transfer serial/parallel conver-
sion register. Data can be set to register SI through registers A and
B with the TSIAB instruction. The contents of register A is transmit-
ted to the low-order 4 bits of register SI, and the contents of
register B is transmitted to the high-order 4 bits of register SI.
During transmission, each bit data is transmitted LSB first from the
lowermost bit (bit 0) of register SI, and during reception, each bit
data is received LSB first to register SI starting from the topmost bit
(bit 7).
When register SI is used as a work register without using serial I/O,
do not select the SCK pin.
(2) Serial I/O transmit/receive completion flag
(SIOF)
Serial I/O transmit/receive completion flag (SIOF) is set to “1” when
serial data transmit or receive operation completes. The state of
SIOF flag can be examined with the skip instruction (SNZSI). Use
the interrupt control register V2 to select the interrupt or the skip
instruction.
The SIOF flag is cleared to “0” when the interrupt occurs or when
the next instruction is skipped with the skip instruction.
(3) Serial I/O start instruction (SST)
When the SST instruction is executed, the SIOF flag is cleared to
“0” and then serial I/O transmission/reception is started.
(4) Serial I/O control register J1
Register J1 controls the synchronous clock, D6/SCK, D5/SOUT and
D4/SIN pin function. Set the contents of this register through regis-
ter A with the TJ1A instruction. The TAJ1 instruction can be used to
transfer the contents of register J1 to register A.
D7 D6 D5 D4 D3 D2 D1 D0
At transmit (D7–D0: transfer data)At receive
D7 D6 D5 D4 D3 D2 D1 D0
SIN pin
SOUT pin
SIN pin
Serial I/O register (SI)
D7 D6 D5 D4 D3 D2 D1 D0
*
D7 D6 D5 D4 D3 D2 D1
D7 D6 D5 D4 D3 D2
D0
D1 D0
Transfer data set
Transfer start
Transfer complete
*
** * * * * *
* * ** ** **
** * * * * *
** ** **
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