參數(shù)資料
型號： M34518M4-XXXSP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP32
封裝： 0.400 INCH, 1.78 MM PITCH, PLASTIC, SDIP-32
文件頁數(shù)： 54/157頁
文件大?。?/td> 1783K
代理商： M34518M4-XXXSP
ML610Q411/ML610Q412/ML610Q415 User’s Manual
Chapter 10
Timers
10 – 20
10.3
Description of Operation
10.3.1
Timer mode operation
The timer counters (TMnC) are set to an operating state (TnSTAT are set to “1”) on the first falling edge of the timer
clocks (TnCK) that are selected by the Timer 0 to 3 control register 0 (TMnCON0) when the TnRUN bits of timer 0 to
3 control register 1 (TMnCON1) are set to “1” and increment the count value on the 2nd falling.
When the count value of TM0 to TM3C and the timer 0 to 3 data register (TMnD) coincide, timer 0 to 3 interrupt
(TMnINT) occurs on the next timer clock falling edge, TMnC are reset to “00H” and incremental counting continues.
When the TnRUN bits are set to “0”, TMnC stop counting after counting once the falling of the timer clock (TnCK).
Confirm that TMnC has been stopped by checking that the TnSTAT bit of the Timer 0–3 control register 1
(TMnCON1) is “0”. When the TnRUN bits are set to “1” again, TMn restart incremental counting from the previous
values. To initialize TMnC to “00H”, perform write operation in TMnC.
The timer interrupt period (TTMI) is expressed by the following equation.
TMnD + 1
TTMI =
TnCK (Hz)
(n = 0 to 3)
TMnD:
Timer 0 to 3 data register (TMnD) setting value (01H to 0FFH)
TnCK:
Clock frequency selected by the Timer 0 to 3 control register 0 (TMnCON0)
After the TnRUN bits are set to “1”, timers are synchronized by the timer clock and counting starts so that an error of a
maximum of 1 clock period occurs until the first timer interrupt. The timer interrupt periods from the second time are
constant.
Figure 10-2 shows the operation timing diagram of Timer 0 to 3.
Figure 10-2
Operation Timing Diagram of Timer 0 to 3
Note:
Even if “0” is written to the TnRUN bits, counting operation continues up to the falling edge (the timer 0 to 3 status
flag (TnSTA) is in a “1” state) of the next timer clock pulse.
Therefore, the timer 0 to 3 interrupt (TMnINT) may
occur.
TMnC
XX
00
88
TMnD
TMnINT
TnSTAT
Write TMnC
TnCK
TnRUN
01
02
87
88
00
62
5F
60
61
01
88
(n = 0 to 3)
TTMI
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