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參數(shù)資料
| 型號： | M34518M4-XXXSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDIP32 |
| 封裝： | 0.400 INCH, 1.78 MM PITCH, PLASTIC, SDIP-32 |
| 文件頁數(shù)： | 110/157頁 |
| 文件大?。?/td> | 1783K |
| 代理商： | M34518M4-XXXSP |
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ML610Q411/ML610Q412/ML610Q415 User’s Manual
Chapter 4
MCU Control Function
4 – 11
4.3
Description of Operation
4.3.1
Program Run Mode
The program run mode is the state where the CPU executes instructions sequentially.
At power-on reset, RESET_N pin reset, low-speed oscillation stop detect reset, or WDT overflow reset, the CPU
executes instructions from the addresses that are set in addresses 0002H and 0003H of program memory (ROM) after
the system reset mode is released.
At reset by the BRK instruction, the CPU executes instructions from the addresses that are set in the addresses 0004H
and 0005H of the program memory after the system reset mode is released. However, when the value of the interrupt
level bit (ELEVEL) of the program status word (PSW) is 02H or higher at execution of the BRK instruction (after the
occurrence of the WDT interrupt or NMI interrupt), the CPU executes instructions from the addresses that are set in the
addresses 0002H and 0003H.
For details of the BRK instruction and PSW, see the “nX-U8/100 Core Instruction Manual” and for the reset function,
see Chapter 3, “Reset Function”.
4.3.2
HALT Mode
The HALT mode is the state where the CPU interrupts execution of instructions and only the peripheral circuits are
running.
When the HLT bit of the standby control register (SBYCON) is set to “1”, the HALT mode is set.
When a NMI interrupt request, a WDT interrupt request, or an interrupt request enabled by an interrupt enable register
(IE1–IE7) is issued, the HLT bit is set to “0” on the falling edge of the next system clock (SYSCLK) and the HALT
mode is returned to the program run mode released.
Figure 4-2 shows the operation waveforms in HALT mode.
CPUCLK
System clock
SYSCLK
Program operating mode
HALT mode
Interrupt request
Program operating mode
SBYCON.HLT
Figure 4-2
Operation Waveforms in HALT Mode
Note:
Since up to two instructions are executed during the period between HALT mode release and a transition to interrupt
processing, place two NOP instructions next to the instruction that sets the HLT bit to “1”.
相關PDF資料 |
PDF描述 |
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| M34519M8-XXXFP | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PDSO42 |
| M34520M8A-XXXFP | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP64 |
| M34520E8-XXXSP | 4-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP64 |
| M34520E8-XXXFP | 4-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PQFP64 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M34518M6-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34518M8-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34519E8FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES |
| M34519M6-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES |
| M34519M8-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:4-BIT CISC SINGLE-CHIP MICROCOMPUTER 720 FAMILY / 4500 SERIES |
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