參數(shù)資料
型號(hào)： M34507M4-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER, PDSO24
封裝： 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁數(shù)： 68/117頁
文件大小： 937K
代理商： M34507M4-XXXFP
Rev.3.01
2005.02.04
page 52 of 111
REJ03B0107-0301
4507 Group
0
1
0
1
0
1
0
1
W21
0
1
Stop (state initialized)
Operating
Instruction clock divided by 4
Instruction clock divided by 16
Stop (state retained)
Operating
Count start synchronous circuit not selected
Count start synchronous circuit selected
Prescaler control bit
Prescaler dividing ratio selection bit
Timer 1 control bit
Timer 1 count start synchronous circuit
control bit
Stop (state retained)
Operating
Count auto-stop circuit not selected
Count auto-stop circuit selected
Count source
Timer 1 underflow signal
Prescaler output (ORCLK)
CNTR input
System clock
Timer 2 control bit
Timer 1 count auto-stop circuit selection
bit (Note 2)
Timer 2 count source selection bits
0
1
0
1
W20
0
1
0
1
W13
W12
W11
W10
Timer control register W1
R/W
at RAM back-up : 00002
at reset : 00002
R/W
at RAM back-up : 00002
at reset : 00002
Timer control register W2
R/W
at RAM back-up : state retained
at reset : 00002
This bit has no function, but read/write is enabled.
Timer 1 underflow signal divided by 2 output
Timer 2 underflow signal divided by 2 output
P12(I/O)/CNTR input (Note 3)
P12 (input)/CNTR input/output (Note 3)
Not used
CNTR output selection bit
P12/CNTR function selection bit
0
1
0
1
0
1
0
1
Timer control register W6
R/W
at RAM back-up : state retained
at reset : 00002
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 1 count start synchronization circuit is selected.
3: CNTR input is valid only when CNTR input is selected as the timer 2 count source.
Q13
Q12
A/D control register Q1
A/D operation mode selection bit
Not used
Analog input pin selection bits
at reset : 00002
at RAM back-up : state retained
0
1
0
1
Q11
0
1
A/D conversion mode
Comparator mode
This bit has no function, but read/write is enabled.
Selected pins
AIN0
AIN1
AIN2
AIN3
Q10
0
1
0
1
R/W
Q11
Q10
W23
W22
W21
W20
W63
W62
W61
W60
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