![](http://datasheet.mmic.net.cn/30000/M32196F8UFP_datasheet_2359476/M32196F8UFP_915.png)
JTAG
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21-11
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
21.5 Boundary Scan Description Language
The Boundary Scan Description Language (abbreviated BSDL) is described in the supplements to the Stan-
dard Test Access Port and Boundary-Scan Architecture of IEEE 1149.1-1990 and IEEE 1149.1a-1993. BSDL
is a subset of IEEE 1076-1993 Standard VHSIC Hardware Description Language (VHDL). BSDL allows to
precisely describe the functions of conforming components to be tested. For package connection test, this
language is used by Automated Test Pattern Generation tools, and for synthesized test logic and verification,
this language is used by Electronic Design Automation tools. BSDL provides powerful extended functions
usable in internal test generation and necessary to write hardware debug and diagnostics software.
The primary section of BSDL has statements of logical port description, physical pin map, instruction set and
boundary register description.
Logical port description
The logical port description assigns meaningful symbol names to each pin on the chip. The logic type of
each pin, whether input, output, input/output, buffer or link, that defines the logical direction of signal flow is
determined here.
Physical pin map
The physical pin map correlates the chip’s logical ports to the physical pins on each package. By using
separate names for each map, it is possible to define two or more physical pin maps in one BSDL descrip-
tion.
Instruction set statement
The instruction set statement writes bit patterns to be shifted in into the chip’s instruction register. This bit
pattern is necessary to place the chip into each test mode defined in standards. Instructions exclusive to the
chip can also be written.
Boundary register description
The boundary register description is a list of boundary register cells or shift stages. Each cell is assigned a
separate number. The cell with number 0 is located nearest to the test data output (JTDO) pin, and the cell
with the largest number is located nearest to the test data input (JTDI) pin. Cells also contain related other
information which includes cell type, logical port corresponding to the cell, logical function of the cell, safety
value, control cell number, disable value and result value.
Note: Boundary Scan Description Language (BSDL) can be downloaded from Renesas Technology
Website after mass production.
21.5 Boundary Scan Description Language