參數(shù)資料
型號: M32182F3TFP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù): 34/36頁
文件大?。?/td> 292K
代理商: M32182F3TFP
2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182Group
Under Development
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
7
Table 3. Description of Pin Function (1/3)
Type
Pin
Name
Input/Output
Function
VCCE
Power supply
-
Power supply (5.0V ± 0.5V or 3.3V ± 0.3V).
EXCVCC
External capaci-
tance connect
-
External capacitance connecting pin.
VCC-BUS
Bus power supply
-
Power supply for the bus control pins (5.0V ± 0.5V or 3.3V ± 0.3V).
VDDE
RAM power supply
-
Internal RAM backup power supply (5.0V ± 0.5V or 3.3V ± 0.3V).
EXCVDD
External capaci-
tance connect
-
Backup power supply for the internal RAM, external capacitance con-
necting pin.
Power
Supply
VSS
Ground
-
Connect all VSS pins to ground (GND).
XIN
Clock input
Input
XOUT
Clock output
Output
Clock input/output pins. These pins contain a PLL-based frequency
multiply-by-8, so input the clock whose frequency is 1/8 the operating
frequency. (XIN input = 10 MHz when CPU clock operates at 80 MHz)
BCLK
System clock
Output
Outputs a clock twice the externally sourced clock frequency, XIN
(when the internal CPU memory clock is 80 MHz, BCLK output = 20
MHz).
Use this output when external sync design is desired.
OSC-VCC
Clock power supply
-
Power supply to the PLL circuit. Connect OSC-VCC to the power supply
OSC-VSS
Clock ground
-
Connect OSC-VSS to ground.
Clock
VCNT
PLL control
-
This pin controls the PLL circuit. Connect a resistor and capacitor to this
pin.
Reset
RESET#
Reset
Input
This pin resets the internal circuits.
These pins set an operation mode.
MOD0
MOD1
Mode
0
Single-chip mode
0
1
Expanded external mode
1
0
Processor mode
(Boot mode) (Note 1)
1
(Do not select)
Mode
MOD0,
MOD1
Mode
Input
Note: In boot mode, the FP pin must be at the high level.
Flash-only
FP
Flash Protect
Input
This pin protects the flash memory against E/W in hardware.
Address
Bus
A11–A30
Address bus
Output
To allow four blocks of up to 2 MB memory space each to be added
externally, 20-bit address (A11–A30) is provided. A31 is not output.
Data bus
DB0–DB15
Data bus
Input/output
This is a 16-bit data bus connecting to an external device. During write
cycle, the microcomputer outputs BHW# or BLW# to indicate the valid
byte write position of the 16-bit data bus. During read cycle, the micro-
computer always reads the full 16-bit data bus. Transferred to the inter-
nal circuit of the M32R, however, is the data at only the valid byte posi-
tion.
CS0#–CS3#
Chip select
Output
Chip select signals for external devices.
RD#
Read
Output
This signal is output when reading external devices.
WR#
Write
Output
This signal is output when writing external devices.
BHW#
Byte High Write
Output
BLW#
Byte Low Write
Output
Indicates the byte positions to which valid are transferred when writing
to external devices. BHW#/ BHE# and BLW#/ BLE# correspond to the
upper address side (DB0–DB7 effective) and the lower address side
(DB8–DB15 effective), respectively.
BHE#
Byte High Enable
Output
For external device access, it indicates that the upper byte data (DB0–
DB7) is valid.
BLE#
Byte Low Enable
Output
For external device access, it indicates that the lower byte data (DB8–
DB15) is valid.
WAIT#
Wait
Input
If WAIT# input is low when the M32R accesses external devices, the
wait cycle extended.
HREQ#
Hold request
Input
This pin is used by an external device to request control of the external
bus. The M32R goes to a hold state when HREQ# input is pulled low.
Bus
Control
HACK#
Hold acknowledge
Output
This signal indicates to the external device that the M32R has entered a
hold state and relinquished control of the external bus.
Note 1: In boot mode, the FP pin must be at the high level.
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