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參數(shù)資料
| 型號： | M32182F3TFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144 |
| 文件頁數(shù)： | 15/36頁 |
| 文件大小： | 292K |
| 代理商： | M32182F3TFP |
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2002-10-11 Rev.1.2
Mitsubishi Microcomputers
32182Group
Under Development
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
22
Built-in 10-Channel DMAC
The microcomputer contains 10 channels of DMAC, allow-
ing for data transfer between internal peripheral I/Os, be-
tween internal RAM and internal peripheral I/O, and be-
tween internal RAMs.
DMA transfer requests can be issued from the user-created
software, as well as can be triggered by a signal generated
by the internal peripheral I/O (A-D converter, timer, or serial
I/O).
The microcomputer also supports cascaded connection
between DMA channels (starting DMA transfer on a chan-
nel at end of transfer on another channel). This makes ad-
vanced transfer processing possible without causing any
additional CPU load.
Table 5. Outline of the DMAC
Item
Content
Number of channels
10 channels
Transfer request
Software trigger
Request from internal peripheral I/O: A-D converter, timer, or serial I/O (reception
completed, transmit buffer empty)
Cascaded connection between DMA channels possible (Note 1)
Maximum number of times transferred
65536 times
Transferable address space
64K bytes (address space from H’0080 0000 to H’0080 FFFF)
Transfers between internal peripheral I/Os, between internal RAM and internal
peripheral IO, and between internal RAMs are supported
Transfer data size
16-bit or 8-bit
Transfer method
Single transfer DMA (control of the internal bus is relinquished for each transfer per-
formed), dual-address transfer
Transfer mode
Single transfer mode
Direction of transfer
One of three modes can be selected for the source and destination of transfer:
Address fixed
Address increment
32-channel ring buffer
Channel priority
Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 > channel 5 > channel
6 > channel 7 > channel 8 > channel 9 (Fixed priority)
Maximum transfer rate
13.3M bytes per second (when internal peripheral clock = 20 MHz)
Interrupt request
Group interrupt request can be generated when each transfer count register under-
flows
Note 1: The following DMA channels can be cascaded.
DMA transfer on channel 1 started at end of one DMA transfer on channel 0
DMA transfer on channel 5 started at completion of all DMA transfers on channel 0 (transfer count register underflow)
DMA transfer on channel 2 started at end of one DMA transfer on channel 1
DMA transfer on channel 0 started at end of one DMA transfer on channel 2
DMA transfer on channel 3 started at end of one DMA transfer on channel 2
DMA transfer on channel 4 started at end of one DMA transfer on channel 3
DMA transfer on channel 6 started at end of one DMA transfer on channel 5
DMA transfer on channel 7 started at end of one DMA transfer on channel 6
DMA transfer on channel 5 started at end of one DMA transfer on channel 7
DMA transfer on channel 8 started at end of one DMA transfer on channel 7
DMA transfer on channel 9 started at end of one DMA transfer on channel 8
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M32182F3UFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
| M32182F3VFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
| M32182F8TFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
| M32182F8TFP#U2 | 制造商:Renesas Electronics Corporation 功能描述:MCU 32-bit M32R RISC 1024KB Flash 5V 144-Pin LQFP |
| M32182F8UFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
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