參數(shù)資料
型號: M32182F3TFP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù): 10/262頁
文件大?。?/td> 3279K
代理商: M32182F3TFP
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁
4
4-12
EIT
32182 Group User’s Manual (Rev.1.0)
4.8 Exception Processing
(4) Branching to the EIT vector entry
The CPU branches to the address H’0000 0020 in the user space. This is the last operation performed in
hardware preprocessing.
(5) Jumping from the EIT vector entry to the user-created handler
The CPU executes the BRA instruction written by the user at the address H’0000 0020 of the EIT vector
entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT
handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack.
Also, save the accumulator and FPSR register as necessary.
(6) Returning from the EIT handler
At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction.
When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time,
the CPU restarts from a word-boundary instruction including the instruction that generated a RIE (see Figure
4.8.1). Except when using reserved instruction exceptions intentionally, occurrence of a reserved instruc-
tion exception suggests that the system has some fatal fault already existing in it. In such a case, therefore,
do not return from the reserved instruction exception handler to the program that was being executed when
the exception occurred.
4.8.2 Address Exception (AE)
[OccurrenceConditions]
Address Exception (AE) occurs when an attempt is made to access a misaligned address in Load or Store
instructions. The following lists the combination of instructions and accessed addresses that may cause
address exceptions to occur.
Two low-order address bits accessed in the LDH, LDUH or STH instruction are ‘01’ or ‘11’
Two low-order address bits accessed in the LD, ST, LOCK or UNLOCK instruction are ‘01,’ ‘10’ or ‘11’
When an address exception occurs, memory access by the instruction that generated the exception is not
performed. If an external interrupt is requested at the same time an address exception is detected, it is the
address exception that is accepted.
[EIT Processing]
(1) Saving SM, IE and C bits
The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC.
BSM
SM
BIE
IE
BC
C
(2) Updating SM, IE and C bits
The PSW register’s SM, IE and C bits are updated as shown below.
SM
Unchanged
IE
0
C
0
(3) Saving the PC
The PC value of the instruction that generated the address exception is set in the BPC register. For ex-
ample, if the instruction that generated the address exception is at address 4, the value 4 is set in the BPC
register. Similarly, if the instruction that generated the address exception is at address 6, the value 6 is set
in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the instruction that
generated the reserved instruction exception resides on a word boundary (BPC register bit 30 = "0") or not on
a word boundary (BPC register bit 30 = "1").
However, in either case of the above, the address to which the RTE instruction returns after the EIT handler
has terminated is address 4. (This is because the 2 low-order address bits are cleared to ‘00’ when returned
to the PC.)
相關(guān)PDF資料
PDF描述
M32182F3VFP 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP144
M32182F3TFP 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
M32196F8UFP 32-BIT, FLASH, 160 MHz, RISC MICROCONTROLLER, PQFP144
M32192F8TFP 32-BIT, FLASH, 160 MHz, RISC MICROCONTROLLER, PQFP144
M32192F8UWG 32-BIT, FLASH, 160 MHz, RISC MICROCONTROLLER, PBGA224
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M32182F3UFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES
M32182F3VFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES
M32182F8TFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES
M32182F8TFP#U2 制造商:Renesas Electronics Corporation 功能描述:MCU 32-bit M32R RISC 1024KB Flash 5V 144-Pin LQFP
M32182F8UFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES