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OVERVIEW
32176 Group User’s Manual (Rev.1.01)
1.2 Block Diagram
Table 1.2.1 Features of the 32176 (1/2)
Functional Block
Features
M32R CPU core
Implementation: Five-stage pipelined instruction processing
Internal 32-bit structure of the core
Register configuration
General-purpose registers: 32 bits × 16 registers
Control registers: 32 bits × 5 registers
Instruction set
16 and 32-bit instruction formats
83 instructions and six addressing modes
Internal multiplier/accumulator (32 bits × 16 bits + 56 bits)
RAM
Capacity: 24 Kbytes
Zero-wait access
The internal RAM can be accessed for reading or rewriting data from the outside independently of
the M32R by using the Real-Time Debugger, without ever causing the CPU performance to
decrease.
Flash memory
Capacity:
M32176F2: 256 Kbytes, M32176F3: 384 Kbytes, M32176F4: 512 Kbytes
Zero-wait access
Durability:
Standard product
: 100 times
10000 (10k) times rewritable
: 4-Kbyte block (Note 2)
: 10,000 (10k) times
-product (Note 1)
: Other blocks
: 1,000 (1k) times
Bus specification
Fundamental bus cycle
: 25 ns (when f(CPUCLK = 40 MHz)
Logical address space
: 4 Gbytes linear
Internal bus specification
: Internal 32-bit data bus (for CPU <-> internal flash memory and RAM access)
: Internal 16-bit data bus (for internal peripheral I/O access)
External area: Maximum 2 Mbytes (during processor mode)
External extention area: Maximum 2 Mbytes
External data address bus: 19-bit address
External data bus: 16-bit data bus
Shortest external bus access: 2 BCLK periods during read, 2 BCLK periods during write
DMAC
Number of channels: 10
Transfers between internal peripheral I/O’s or internal RAM’s or between internal peripheral I/O
and internal RAM are supported.
Capable of advanced DMA transfers when used in combination with internal peripheral I/O
Transfer request: Software or internal peripheral I/O (A-D converter, MJT, serial I/O or CAN)
DMA channels can be cascaded. (DMA transfer on a channel can be started by completion of a
transfer on another channel.)
Interrupt request: DMA transfer counter register underflow
Multijunction timer (MJT)
37-channel multi-functional timer
16-bit output related timer × 11 channels, 16-bit input/output related timer × 10 channels,
16-bit input related timer × 8 channels, 32-bit input related timer × 8 channels
Flexible timer configuration is possible by interconnecting these timer channels.
Interrupt request: Counter underflow or overflow and rising or falling or both edges or high or low level
from the TIN pin (These can be used as external interrupt inputs irrespective of timer operation.)
DMA transfer request: Counter underflow or overflow and rising or falling or both edges or high or
low level from the TIN pin (These can be used as external DMA transfer request inputs
irrespective of timer operation.)
Note 1: The 10000 (10k) times rewritable product is offered as an optional item. For details about it, please contact your
nearest office of Renesas or its distributor.
Note 2: Block 1: H’0000 2000 to H’0000 2FFFF
Block 2: H’0000 3000 to H’0000 3FFFF