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32170/32174 Group User's Manual (Rev. 2.1)
11.4 Precautions on Using A-D Converters
Forcible termination during scan operation
If A-D conversion is halted by setting the A-D conversion stop bit (AD0CSTP, AD1CSTP) to 1
during scan mode operation and you read the content of the A-D data register for the channel in
which conversion was in progress, it shows the last conversion result that had been transferred to
the A-D data register before the conversion was forcibly terminated.
_____
ADTRG signal and input/output port
_____
If you selected the ADTRG signal for an A-D conversion start trigger, do not use the ADTRG pin
as an input/output port (P67).
Modification of A-D converter related registers
If you want to change the contents of the A-D Conversion Interrupt Control Register, each Single
and Scan Mode Register, or A-D Successive Approximation Register, except for the A-D
conversion stop bit, do your change while A-D conversion is inactive, or be sure to restart A-D
conversion after you changed the register contents. If the contents of these registers are
changed in the middle of A-D conversion, the conversion results cannot be guaranteed.
Handling of analog input signals
The A-D converters included in the 32170 do not have a sample-and-hold circuit. Therefore,
make sure the analog input levels are fixed during A-D conversion.
A-D conversion completion bit readout timing
If you want to read the A-D conversion completion bit (Single Mode Register 0's D5 bit or Scan
Mode Register 0's D5 bit) immediately after A-D conversion has started, be sure to adjust the
timing one clock cycle by, for example, inserting a NOP instruction before you read.
Regarding analog input pins
Figure 11.4.1 shows an internal equivalent circuit of the analog input unit. For A-D conversions to
be performed correctly, the microcomputer must finish charging the internal capacitor C2 within
the designated time (i.e., the sampling time). Make sure the conditions shown below are met
when determining the analog output device’s output impedance and the value of an external
stabilizing capacitor.
Condition 1: Sampling time (
) > C1
× R1
Condition 2: The peak current of i2 be minimized.
A-D CONVERTERS
11.4 Precautions on Using A-D Converters
AD conversion time
10
× 4