
9
9-3
32170/32174 Group User's Manual (Rev. 2.1)
DMAC
9.1 Outline of the DMAC
Figure 9.1.1 Block Diagram of the DMAC
DMA
request
selector
A-D0 conversion completed
DMA channel 0
Software start
MJT (TIN13 input signal)
One DMA0 transfer completed
Internal
bus
Software start
Serial I/O0 (reception completed)
One DMA2 transfer completed
One DMA3 transfer completed
MJT (TIO8_udf)
MJT (input event bus 2)
MJT (output event bus 0)
MJT (TIN19 input signal)
Software start
MJT (TIN18 input signal)
One DMA1 transfer completed
MJT (output event bus 1)
Software start
Serial I/O0 (transmit buffer empty)
Serial I/O1 (reception completed)
Source address
register
Destination address
register
Determination block
DMA start
MJT (TIN0 input signal)
All DMA0 transfers completed (udf)
Software start
MJT (TIN1 input signal)
One DMA5 transfer completed
Software start
One DMA7 transfer completed
Serial I/O2 (reception completed)
MJT (TIN20 input signal)
Serial I/O1 (transmit buffer empty)
Software start
MJT (TIN2 input signal)
One DMA6 transfer completed
Serial I/O2 (transmit buffer empty)
Software start
MJT (input event bus 0)
Serial I/O3 (reception completed)
MJT (TIN7 input signal)
Source
Destination
Transfer count
Interrupt
request
Internal bus arbitration
Software start
MJT (TIN8 input signal)
One DMA8 transfer completed
Serial I/O3 (transmit buffer empty)
Transfer count
register
udf
DMA
request
selector
DMA channel 1
udf
Source
Destination
Transfer count
DMA
request
selector
DMA channel 2
udf
Source
Destination
Transfer count
DMA
request
selector
DMA channel 3
udf
Source
Destination
Transfer count
DMA
request
selector
DMA channel 4
udf
Source
Destination
Transfer count
DMA
request
selector
DMA channel 5
udf
Source
Destination
Transfer count
DMA
request
selector
DMA channel 6
udf
Source
Destination
Transfer count
DMA
request
selector
DMA channel 7
udf
Source
Destination
Transfer count
DMA
request
selector
DMA channel 8
udf
Source
Destination
Transfer count
DMA
request
selector
DMA channel 9
udf
Determination block
DMA start
Internal bus arbitration
Interrupt
request