
3
3-17
Rev.1.0
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
H’0080 0800
H’0080 0802
H’0080 0804
H’0080 0850
H’0080 0880
H’0080 0882
H’0080 088A
H’0080 0890
H’0080 0892
H’0080 0894
H’0080 0896
H’0080 0898
H’0080 089A
H’0080 089C
H’0080 089E
H’0080 08A4
D0
D7 D8
D15
H’0080 08A0
H’0080 08A6
H’0080 00A8
H’0080 08AA
H’0080 08AC
H’0080 08AE
H’0080 08E0
H’0080 08E2
H’0080 08E4
H’0080 08E6
H’0080 08E8
H’0080 08EA
H’0080 08F2
H’0080 08F4
H’0080 08F6
H’0080 08F8
H’0080 0846
H’0080 0848
H’0080 084A
H’0080 0844
H’0080 0842
H’0080 0840
H’0080 08A2
TML0 Counter H (TML0CTH)
TML0 Counter L (TML0CTL)
Input Processing Control Register 0 (TINCR0)
Input Processing Control Register 1 (TINCR1)
Input Processing Control Register 2 (TINCR2)
Input Processing Control Register 3 (TINCR3)
Input Processing Control Register 4 (TINCR4)
Input Processing Control Register 5 (TINCR5)
TIN Interrupt Status Register 0 (TINIST0)
TIN Interrupt Mask Register 0 (TINIMA0)
TIN Interrupt Status Register 1 (TINIST1)
TIN Interrupt Mask Register 1 (TINIMA1)
TIN Interrupt Status Register 2 (TINIST2)
TIN Interrupt Mask Register 2 (TINIMA2)
TIN Interrupt Status Register 3 (TINIST3)
TIN Interrupt Mask Register 3 (TINIMA3)
TIN Interrupt Status Register 4 (TINIST4)
TIN Interrupt Mask Register 4 (TINIMA4)
TIN Interrupt Status Register 5 (TINIST5)
TIN Interrupt Mask Register 5 (TINIMA5)
TIN Interrupt Status Register 8 (TINIST8)
TIN Interrupt Mask Register 8 (TINIMA8)
TML0 Control Register 0 (TML0CR)
Prescaler 1 (PRS1)
TML0 Measurement 3 Register H (TML0MR3H)
TML0 Measurement 3 Register L (TML0MR3L)
TML0 Measurement 2 Register H (TML0MR2H)
TML0 Measurement 2 Register L (TML0MR2L)
TML0 Measurement 1 Register H (TML0MR1H)
TML0 Measurement 1 Register L (TML0MR1L)
TML0 Measurement 0 Register H (TML0MR0H)
TML0 Measurement 0 Register L (TML0MR0L)
TML0 Old Measurement 3 Register H (TML0OLDMR3H)
TML0 Old Measurement 3 Register L (TML0OLDMR3L)
TML0 Old Measurement 2 Register H (TML0OLDMR2H)
TML0 Old Measurement 2 Register L (TML0OLDMR2L)
TML0 Old Measurement 1 Register H (TML0OLDMR1H)
TML0 Old Measurement 1 Register L (TML0OLDMR1L)
TML0 Old Measurement 0 Register H (TML0OLDMR0H)
TML0 Old Measurement 0 Register L (TML0OLDMR0L)
TMS0 Old Measurement 3 Register (TMS0OLDMR3)
TMS0 Old Measurement 2 Register (TMS0OLDMR2)
TMS0 Old Measurement 1 Register (TMS0OLDMR1)
TMS0 Old Measurement 0 Register (TMS0OLDMR0)
TMS0 Counter (TMS0CT)
TMS0 Measurement 3 Register (TMS0MR3)
TMS0 Measurement 2 Register (TMS0MR2)
TMS0 Measurement 1 Register (TMS0MR1)
TMS0 Measurement 0 Register (TMS0MR0)
TMS0 Control Register (TMS0CR)
Prescaler (PRS0)
+0 address
+1 address
Address
Blank areas are reserved for future use.
Figure 3.4.9 Register Mapping of the SFR Area (6)