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CHAPTER 10 INPUT/OUTPUT TIMERS
10.1 Outline of the Input/Output Timers ....................................................................... 10-2
10.2 Common Timer Unit ............................................................................................. 10-8
10.2.1 Register Map of the Common Timer Unit ......................................... 10-8
10.2.2 Prescaler Unit ................................................................................... 10-10
10.2.3 Input Processing Control Unit ........................................................... 10-11
10.2.4 Output Flip-flop Control Unit ............................................................. 10-20
10.2.5 Interrupt Control Unit ........................................................................ 10-24
10.3 TMS (Input Related 16-bit Timers) ...................................................................... 10-43
10.3.1 Outline of the TMS ........................................................................... 10-43
10.3.2 Functional Outline of the TMS .......................................................... 10-43
10.3.3 TMS Related Register Map .............................................................. 10-45
10.3.4 TMS Control Register ....................................................................... 10-46
10.3.5 TMS Counter (TMS0CT) .................................................................. 10-47
10.3.6 TMS Measure Registers (TMS0MR3~0) .......................................... 10-48
10.3.7 TMS Old Measure Registers (TMS0OLDMR3~0) ............................ 10-49
10.3.8 Operation of TMS Measure Input ..................................................... 10-50
10.4 TML (Input Related 32-bit Timers) ....................................................................... 10-52
10.4.1 Outline of the TML ............................................................................ 10-52
10.4.2 Functional Outline of the TML .......................................................... 10-53
10.4.3 TML Related Register Map .............................................................. 10-54
10.4.4 TML Control Register ....................................................................... 10-55
10.4.5 TML Counters ................................................................................... 10-56
10.4.6 TML Measure Registers ................................................................... 10-57
10.4.7 TML Old Measure Registers ............................................................ 10-58
10.4.8 Operation of TML Measure Input ..................................................... 10-59
10.5 TID (Input Related 16-bit Timers) ........................................................................ 10-61
10.5.1 Outline of the TID ............................................................................. 10-61
10.5.2 TID Related Register Map ................................................................ 10-63
10.5.3 TID Control & Prescaler Enable Registers ....................................... 10-64
10.5.4 TID Counters (TID0CT and TID1CT) ............................................... 10-66
10.5.5 TID Reload Registers (TID0RL and TID1RL) ................................... 10-67
10.5.6 Outline of Each TID Operation Mode ............................................... 10-68
10.6 TOM (Output Related 16-bit Timers) ................................................................... 10-75
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