20
20-10
32170/32174 Group User's Manual (Rev. 2.1)
20.3.2 Power-Shutdown Sequence When Using RAM Backup
The diagram below shows a power-shutdown sequence (5.0 V, 3.3 V power supply) of the M32R/
ECU when using RAM backup.
Figure 20.3.3 Power-Shutdown Sequence When Using RAM Backup(when VCC=5V)
VCCE
AVCC0,
AVCC1
VREF0,
VREF1
P72 / HREQ
RESET
VDD
VCCI
FVCC
OSC-VCC
5V
3.3V
0V
2.0V
(b)
(a)
(c)
(d)
(a):
__________
Pull the HREQ pin input low to halt the CPU at end of bus cycle. Or disable RAM access in
software. The M32R/ECU allows P72 to be used as HREQ irrespective of its operation
mode.
(b):
____________
With the CPU halted, pull the RESET pin input low. Or while RAM access is disabled, pull
____________
the RESET pin input low.
(c):
____________
Turn off the 5 V and the 3.3 V power supply after the RESET pin goes low.
(d): Reduce the VDD voltage from 3.3 V to 2.0 V as necessary.
Note: Power-shutdown requirements
VDD
VCCI
FVCC
OSC-VCC
VCCI
POWER-ON/POWER-SHUTDOWN SEQUENCE
20.3 Power-Shutdown Sequence
Note: Inversion of phases may not cause a problem providing the difference in voltage levels (about 0.1 to
0.2 V in a transient state) is within the safe region where current inflow due to diode characteristics do
not occur. For stable operation, however, make sure the recommended operating conditions are met
when designing the application circuit.
