參數(shù)資料
型號: M308B8SGP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 32 MHz, MICROCONTROLLER, PQFP144
封裝: 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件頁數(shù): 54/70頁
文件大小: 1150K
代理商: M308B8SGP
58
XMEGA D4 [DATASHEET]
8135P–AVR–01/2014
SPM
Z+
Store Program Memory and Post-Increment
by 2
(RAMPZ:Z)
Z
R1:R0,
Z + 2
None
-
IN
Rd, A
In From I/O Location
Rd
I/O(A)
None
1
OUT
A, Rr
Out To I/O Location
I/O(A)
Rr
None
1
PUSH
Rr
Push Register on Stack
STACK
Rr
None
POP
Rd
Pop Register from Stack
Rd
STACK
None
XCH
Z, Rd
Exchange RAM location
Temp
Rd
(Z)
Rd,
(Z),
Temp
None
2
LAS
Z, Rd
Load and Set RAM location
Temp
Rd
(Z)
Rd,
(Z),
Temp v (Z)
None
2
LAC
Z, Rd
Load and Clear RAM location
Temp
Rd
(Z)
Rd,
(Z),
($FFh – Rd)
(Z)
None
2
LAT
Z, Rd
Load and Toggle RAM location
Temp
Rd
(Z)
Rd,
(Z),
Temp
(Z)
None
2
Bit and bit-test instructions
LSL
Rd
Logical Shift Left
Rd(n+1)
Rd(0)
C
Rd(n),
0,
Rd(7)
Z,C,N,V,H
1
LSR
Rd
Logical Shift Right
Rd(n)
Rd(7)
C
Rd(n+1),
0,
Rd(0)
Z,C,N,V
1
ROL
Rd
Rotate Left Through Carry
Rd(0)
Rd(n+1)
C
C,
Rd(n),
Rd(7)
Z,C,N,V,H
1
ROR
Rd
Rotate Right Through Carry
Rd(7)
Rd(n)
C
C,
Rd(n+1),
Rd(0)
Z,C,N,V
1
ASR
Rd
Arithmetic Shift Right
Rd(n)
Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)
Rd(7..4)
None
1
BSET
s
Flag Set
SREG(s)
1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s)
0
SREG(s)
1
SBI
A, b
Set Bit in I/O Register
I/O(A, b)
1
None
1
CBI
A, b
Clear Bit in I/O Register
I/O(A, b)
0
None
1
BST
Rr, b
Bit Store from Register to T
T
Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b)
T
None
1
SEC
Set Carry
C
1
C
1
CLC
Clear Carry
C
0
C
1
SEN
Set Negative Flag
N
1
N
1
CLN
Clear Negative Flag
N
0
N
1
SEZ
Set Zero Flag
Z
1
Z
1
CLZ
Clear Zero Flag
Z
0
Z
1
SEI
Global Interrupt Enable
I
1
I
1
CLI
Global Interrupt Disable
I
0
I
1
Mnemonics
Operands
Description
Operation
Flags
#Clocks
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