參數(shù)資料
型號： M306V8FJFP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP116
封裝： 20 X 20 MM, 0.65 MM PITCH, PLASTIC, LQFP-116
文件頁數(shù)： 33/77頁
文件大?。?/td> 2650K
代理商： M306V8FJFP
M306V8FJFP
Rev.1.31
Apr 18, 2005
page 37 of 363
REJ03B0082-0131
Table 4.7. Microcomputer Status in Hold State
Item
Status
BCLK
Output
_______
_____
________
_________ _______ _______
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH, WR, BHE
High-impedance
I/O ports
P0, P1, P3, P4(Note 1)
High-impedance
P6 to P10
Maintains status when hold signal is received
__________
HLDA
Output “L”
Internal peripheral circuits
ON (but watchdog timer stops)
ALE signal
Indeterminate
__________
HOLD > DMAC > CPU
__________
(7) HOLD Signal
This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the
__________
input on HOLD pin is pulled low, the microcomputer is placed in a hold state after the bus access then in
__________
process finishes. The microcomputer remains in the hold state while the HOLD pin is held low, during
__________
which time the HLDA pin outputs a low-level signal.
Table 4.7 shows the microcomputer status in the hold state.
__________
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence. However,
if the CPU is accessing an odd address in word units, the DMAC cannot gain control of the bus during two
separate accesses.
Figure 4.8. Bus-using Priorities
Note 1: When I/O port function is selected.
(8) BCLK Output
If the PM07 bit in the PM0 register is set to “0” (output enable), a clock with the same frequency as
that of the CPU clock is output as BCLK from the BCLK pin.
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