參數(shù)資料
型號(hào)： M306NNMG-XXXGP
元件分類： 微控制器/微處理器
英文描述： 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP128
封裝： 14 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-128
文件頁(yè)數(shù)： 68/72頁(yè)
文件大?。?/td> 649K
代理商： M306NNMG-XXXGP
REVISION HISTORY
M16C/6N Group (M16C/6NL, M16C/6NN) Data Sheet
Rev.
Date
Description
Page
Summary
A-1
1.00 Jul. 20, 2004
1.01 Nov. 01, 2004
1.02 Jul. 01, 2005
2.10 Aug.25, 2006
–
First edition issued
–
Revised edition issued
* Revised parts and revised contents are as follows (except for expressional change).
26
Table 5.2 Recommended Operating Conditions (1)
IOH(peak): Unit is revised from “V” to “mA”.
27
Table 5.3 Recommended Operating Conditions (2)
NOTE 3: “VCC = 3.0 ± 0.3 V” is revised to “VCC = 3.3 ± 0.3 V”.
28
Table 5.4 IIH, IIL: “P3_3” is revised to “P3_7” in Parameter.
31
Table 5.9: VCC = 3.0 ± 0.3 V” is revised to “VCC = 3.3 ± 0.3 V” in Flash Program, Erase
Voltage.
–
Revised edition issued
* Revised parts and revised contents are as follows (except for expressional change).
5
Table 1.3 Product List is revised.
13
FIgure 4.1 SFR Information (1): The value of After Reset in CM2 Register is revised.
19
Figure 4.7 SFR Information (7): NOTE 1 is revised.
28
Table 5.4 Electrical Characteristics (1)
Measuring Condition of VOL is revised from “LOL = –200A” to “LOL = 200A”.
29
Table 5.5 Electrical Characteristics (2): Mask ROM (5th item)
“f(XCIN)” is changed to “(f(BCLK)).
30
Table 5.6 A/D Conversion Characteristics: “Tolerance Level Impedance” is deleted.
–
Revised edition issued
* Memory expansion and microprocessor modes are added.
* Revised parts and revised contents are as follows (except for expressional change).
2
Table 1.1 Fuictions and Specifications for M16C/6N Group (100-pin version)
Operating Mode is revised.
3
Table 1.2 Fuictions and Specifications for M16C/6N Group (128-pin version)
Operating Mode is revised.
5
Table 1.3 Product Information
Status of development is revised and NOTES 1 and 2 are added.
6
Figure 1.3 Pin Assignments (1): Bus control pins are added.
7, 8
Tables 1.4 and 1.5 List of Pin Names for 100-pin package (1)(2) are added.
9
Figure 1.4 Pin Assignments (2): Bus control pins are added.
10 to 12
Tables 1.6 to 1.8 List of Pin Names for 128-pin package (1)(2)(3) are added.
13 to 15
Tables 1.9 to 1.11 Pin Functions (1)(2)(3) are revised.
18
3. Memory: Last sentence (In memory expansion ...) is added.
Figure 3.1 Memory Map: NOTES 1 and 2 are added.
19
Table 4.1 SFR Information (1)
Value of After Reset in PM0 is revised.
CSR Register is added to 0008h.
CSE Register is added to 001Bh.
NOTE 1 is added.
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