
A-D Converter
Rev.1.00
Jun 06, 2003
page 139 of 290
M16C/6K9 Group
Item
Specification
Function
All pins perform repeat sweep A-D conversion, with emphasis on the pin or
pins selected by the A-D sweep pin selection bits
Example : AN0 selected
AN0
AN1
AN0
AN2
AN0
AN3, etc
Start condition
Writing “1” to A-D conversion start flag
Stop condition
Writing “0” to A-D conversion start flag
Interrupt request generation timing
Not generated
Input pin
AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins)
Reading of result of A-D converter
Read A-D registers corresponding to selected pins (at any time)
(5) Repeat sweep mode 1
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using
the A-D sweep pin selection bits. Table.JA-6 shows the specifications of repeat sweep mode 1. Fig.JA-8
shows the A-D control register in repeat sweep mode 1.
Fig.JA-8 A-D conversion register in repeat sweep mode 1
Table.JA-6 Repeat sweep mode 1 specifications
A-D control register 0 (Note)
Symbol
Address
When reset
ADCON0
03D616
00000XXX2
b7
b6
b5
b4
b3
b2
b1
b0
Analog input pin selection bits
CH0
Bit symbol
Bit name
Function
CH1
CH2
A-D operation mode selection
bits 0
1 1 : Repeat sweep mode 1
MD0
MD1
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
ADST
A-D conversion start flag
0 : A-D conversion disabled
1 : A-D conversion started
W
R
A-D control register 1 (Note 1)
Symbol
Address
When reset
ADCON1
03D716
0016
Bit name
Function
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
A-D sweep pin selection bits
SCAN0
SCAN1
MD2
BITS
8/10-bit mode selection bit
0 : 8-bit mode
1 : 10-bit mode
VCUT
OPA0
Vref connect bit
1 : Repeat sweep mode 1
OPA1
A-D operation mode selection
bit 1
1 : Vref connected
W
R
1 1
Invalid in repeat sweep mode 1
1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
b4 b3
When repeat sweep mode 1 is selected
0 0 : AN0 (1 pin)
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
b1 b0
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : Inhibited
b7 b6
1
Note: If the A-D control register is rewritten during A-D conversion, the conversion result
is indeterminate.
ANEX0,1 selection bis
CKS0
Frequency selection bit 0
0 : FAD/4 selected
1 : FAD/2 selected
CKS1
Frequency selection bit 1
0 : FAD/2 or FAD/4 selected
1 : FAD selected