參數(shù)資料
型號(hào)： M30622MEP-XXXFP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機(jī)
文件頁(yè)數(shù)： 38/87頁(yè)
文件大?。?/td> 901K
代理商： M30622MEP-XXXFP
M16C/62 Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics (M16C/62P)
4
8
f
3
0
0
2
,
0
.
o
N
0
1
e
R
page 38
V
CC1
= V
CC2
= 5V
Timing Requirements
(V
CC1
= V
CC2
= 5V, V
SS
= 0V, at Topr = – 20 to 85
o
C / – 40 to 85
o
C unless otherwise specified)
Table 5.14 Memory Expansion Mode and Microprocessor Mode
Max.
External clock rise time
External clock fall time
ns
ns
t
r
t
f
Min.
62.5
25
25
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
ns
ns
ns
t
c
t
w(H
)
t
w(L)
Parameter
Symbol
Unit
Standard
15
15
Table 5.13 External Clock Input (XIN input)
(Note 1)
(Note 2)
(Note 3)
40
30
40
0
0
0
1. Calculated according to the BCLK frequency as follows:
0.5 X 10
9
[ns]
Min.
Data input setup time
RDY input setup time
HOLD input setup time
ns
ns
ns
t
su(DB-RD)
t
su(RDY-BCLK )
t
su(HOLD-BCLK )
Parameter
Symbol
Unit
Max.
Standard
Data input hold time
RDY input hold time
HOLD input hold time
ns
ns
ns
t
h(RD-DB)
t
h(BCLK -RDY)
t
h(BCLK-HOLD )
Data input access time (for setting with no wait)
Data input access time (for setting with wait)
Data input access time (when accessing multiplex bus area)
ns
ns
ns
t
ac1(RD-DB)
t
ac2(RD-DB)
t
ac3(RD-DB)
f(BCLK)
–
45
2. Calculated according to the BCLK frequency as follows:
(n
–
0.5) X 10
9
f(BCLK)
–
45
[ns]
3. Calculated according to the BCLK frequency as follows:
(n
–
0.5) X 10
9
f(BCLK)
–
45
[ns]
n is
“
2
”
for 1-wait setting,
“
3
”
for 2-wait setting and
“
4
”
for 3-wait
setting.
n is
“
2
”
for 2-wait setting,
“
3
”
for 3-wait setting.
NOTES:
相關(guān)PDF資料
PDF描述
M30622MEP-XXXGP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
M30622MGP-XXXFP SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
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參數(shù)描述
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M30622MGP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
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