參數(shù)資料
型號： M30622MAP-XXXFP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機(jī)
文件頁數(shù)： 42/87頁
文件大小： 901K
代理商： M30622MAP-XXXFP
M16C/62 Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics (M16C/62P)
4
8
f
3
0
0
2
,
0
.
o
N
0
1
e
R
page 42
Table 5.28 Memory Expansion and Microprocessor Modes
(for 1- to 3-wait setting and external area access)
y
m
b
o
l
P
r
a
(
B
C
L
K
-
A
D
)
A
d
r
e
s
s
o
u
t
p
u
t
d
e
l
a
y
t
i
m
t
h
(
B
C
L
K
-
A
D
)
A
d
r
e
s
s
o
u
t
p
u
t
h
o
l
d
t
i
m
e
t
h
(
R
D
-
A
D
)
A
d
r
e
s
s
o
u
t
p
u
t
h
o
l
d
t
i
m
e
t
h
(
W
R
-
A
D
)
A
d
r
e
s
s
o
u
t
p
u
t
h
o
l
d
t
i
m
e
V
CC1
= V
CC2
= 5V
Switching Characteristics
(V
CC1
= V
CC2
= 5V, V
SS
= 0V, at Topr = – 20 to 85
o
C / – 40 to 85
o
C unless otherwise specified)
S
Standard
M
i
n
.
Measuring condition
M
2
a
x
.
a
m
e
t
e
r
U
n
i
t
t
d
d
d
d
d
e
5
n
n
n
n
s
s
s
s
(
(
(
r
r
r
e
e
e
f
f
f
e
e
e
r
r
r
s
s
s
t
t
t
o
o
o
B
R
W
C
D
R
L
)
)
K
)
4
0
t
h
t
d
t
h(BCLK-ALE)
t
d
(
B
C
L
t
h
(
B
C
L
t
d(BCLK-WR)
t
h(BCLK-WR)
t
d
(
B
C
L
t
h(BCLK-DB)
t
d(DB-WR)
(
B
C
L
K
-
C
S
)
C
A
ALE signal output hold time
R
s
i
g
n
a
l
o
u
t
p
R
s
i
g
n
a
l
o
u
t
p
WR signal output delay time
WR signal output hold time
D
t
a
o
u
t
p
u
t
d
e
Data output hold time (refers to BCLK)
(3)
Data output delay time (refers to WR)
h
L
i
E
p
s
s
e
i
g
l
n
e
c
a
t
l
o
o
u
u
t
p
p
u
u
t
d
h
o
e
l
a
d
t
i
t
m
i
m
e
(
r
e
f
e
r
s
t
o
B
C
L
K
)
4
n
n
ns
n
n
ns
ns
n
ns
ns
s
s
(
B
C
L
K
-
A
L
E
)
t
t
l
y
e
15
–
4
K
-
R
D
)
D
D
u
u
t
t
d
h
e
o
l
l
a
d
y
i
t
m
i
m
e
e
2
5
s
s
K
-
R
D
)
t
0
25
0
K
-
D
B
)
a
l
a
y
t
i
m
e
(
r
e
f
e
r
s
t
o
B
C
L
K
)
4
0
s
4
t
h(WR-DB)
t
d(BCLK-HLDA)
Data output hold time (refers to WR)
(3)
HLDA output delay time
ns
n
1. Calculated according to the BCLK frequency as follows:
4
0
f(
B
C
L
K
)
(n
–
0.5) X 10
9
–
[ns]
t
d
(
B
C
L
K
-
C
S
)
C
h
i
p
s
e
l
e
c
t
o
u
t
p
u
t
d
e
l
a
y
t
i
m
e
2
5
n
s
(Note 2)
3. This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t =
–
CR X ln (1
–
V
OL
/ V
CC2
)
by a circuit of the right figure.
For example, when V
OL
= 0.2V
CC2
, C = 30pF, R = 1k
, hold time
of output
“
L
”
level is
t =
–
30pF X 1k
X ln (1
–
0.2V
CC2
/ V
CC2
)
= 6.7ns.
DBi
R
C
(Note 1)
(Note 2)
2. Calculated according to the BCLK frequency as follows:
.
5
X
1
0
9
[n
s
f(
B
C
L
K
)
0
]
n
s
W
i
s
t
h
i
e
“
n
n
1
g
”
n
f
a
=
o
n
r
d
1
1
,
-
“
f
w
3
(
B
a
f
C
i
o
L
t
r
s
K
e
3
)
t
-
t
w
i
s
i
n
a
g
i
1
,
2
s
.
“
2
e
5
”
t
t
f
i
H
o
n
r
g
z
.
2
-
w
a
i
t
e
t
”
t
M
o
r
l
e
s
s
.
–
10
NOTES:
4
0
s
See
Figure 5.1
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M30622MAP-XXXGP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
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