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M16C/28 Group
Under development Preliminary specification
Specifications in this manual are tentative and subject to change.
19. Flash Memory Version
Rev.0.60 2004.02.01
page 337 of N
REJ09B0047-0060Z
Note 1: When setting this bit to “1”, set to “1” immdediately after setting it first to “0”. Do not generate an
interrupt or a DMA transfer between setting the bit to “0” and setting it to “1”. Set this bit while the
P85/NMI/SD pin is “H” when selecting the NMI function. Set by program in a space other than the
flash memory in EW0 mode. Set this bit to read alley mode and “0”
Note 2: Set this bit to “1” immediately after setting it first to “0” while the FMR01 bit is set to “1”. Do not
generate an interrupt or a DMA transfer between setting this bit to “0” and setting it to “1”.
Note 3: Set this bit by a program in a space other than the flash memory.
Note 4: This bit is set to “0” by executing the clear status command.
Note 5: This bit is enabled when the FMR01 bit is set to “1” (CPU rewrite mode). This bit can be set to
“1” when the FMR01 bit is set to “1”. However, the flash memory does not enter low-power
consumption status and it is not initialized.
Flash memory control register 0
Symbol
Address
After reset
FMR0
01B716
XX0000012
b7
b6
b5
b4
b3
b2 b1
b0
FMR00
Bit symbol
Bit name
Function
RW
0: Busy (during writing or erasing)
1: Ready
CPU rewrite mode select bit
(Note1)
0: Disables CPU rewrite mode
(Disables software command)
1: Enables CPU rewrite mode
(Enables software commands)
FMR01
Block 0, 1 rewrite enable bit
(Note 2)
Set write protection for user ROM area
(see Table 19.5.2.1)
Flash memory stop bit
(Note 3, 5)
FMR02
FMSTP
0
RY/BY status flag
Reserved bit
Set to “0”
0: Terminated normally
1: Terminated in error
Program status flag
FMR06
0: Terminated normally
1: Terminated in error
Erase status flag
FMR07
RW
RO
(b5-b4)
0: Starts flash memory operation
1: Stops flash memory operation
(Enters low-power consumption state
and flash memory reset)
0
(Note 4)
Flash memory control register 1
Symbol
Address
After reset
FMR1
01B516
000XXX0X2
b7
b6
b5
b4
b3
b2 b1
b0
Bit symbol
Bit name
Function
EW1 mode select bit (Note1)
0: EW0 mode
1: EW1 mode
FMR11
Block A, B access wait bit (
Note 3)
Reserved bit
When read, its content is indeterminate
Reserved bit
Set to “0”
Nothing is assigned. When write, set to “0”.
When read, its contect is indeterminate.
0
RW
RO
RW
(b0)
(b4)
Reserved bit
(b3-b2)
RO
Note 1: Set this bit to “1” immediately after setting it first to “0”. Do not generate an interrupt or a DMA
transfer between setting the bit to “0” and setting it to “1”. Set this bit while the P85/NMI/SD pin is “H”
when the NMI function is selected. If the FMR01 bit is set to “0”, the FMR01 bit and FMR11 bit are
both set to “0”
Note 2: Set this bit to “1” immediately after setting it first to “0”. Do not generate an interrupt or a DMA
transfer after setting to “0”.
Note 3: When rewriting more than 100 times, set this bit to “1” (with wait state). When the FMR17 bit is “1”
(with wait state), regardless of the content of the PM17 bit, 1 wait is inserted at the access to the
block A and B.
(b5)
FMR16
RW
Block 0 to 3 rewrite enable
bit (Note2)
FMR17
Set write protection for user ROM area
(see Table 19.5.2.1)
0: Disable
1: Enable
0: PM17 enabled
1: With wait state (1 wait)
When read, its content is indeterminate
Figure 19.5.1. Flash memory control register 0,1