
105
Specifications in this manual are tentative and subject to change
Rev. E
MITSUBISHI MICROCOMPUTERS
M30245 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
Transfer modes
Single transfer mode
DMA transfer occurs until the tranfer counter underflows. Afterward, the DMA becomes inactive
Repeat transfer mode
The DMA remains active even after the transfer counter underflows. The transfer counter and forward
direction address pointer are reloaded after each transfer counter underflow. The DMA becomes inactive
when "0" is written to the DMA enable bit.
DMA enable bit
Setting the DMA enable bit to “1” makes the DMAC active. The DMAC carries out the following operations
at the time data transfer starts immediately after DMAC is turned active.
(1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the
forward direction - to the forward direction address pointer.
(2) Reloads the value of the transfer counter reload register to the transfer counter.
Thus overwriting “1” to the DMA enable bit with the DMAC being active carries out the operations given
above, so the DMAC operates again from the initial state at the instant “1” is overwritten to the DMA enable
bit.
DMA request bit
The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of
DMA request factors for each channel.
DMA request factors include the following.
Factors effected by using the interrupt request signals from the built-in peripheral functions and software
DMA factors (internal factors) effected by a program.
External factors effected by utilizing the input from external interrupt signals.
For the selection of DMA request factors, see the descriptions of the DMAi request cause select registers.
The DMA request bit turns to “1” if the DMA transfer request signal occurs regardless of the DMAC’s state
(regardless of whether the DMA enable bit is set “1” or to “0”). It turns to “0” immediately before data
transfer starts.
In addition, it can be set to “0” by use of a program, but cannot be set to “1”.
There can be instances in which a change in DMA request factor selection bit causes the DMA request bit
to turn to “1”. Make sure to set the DMA request bit to “0” after the DMA request factor selection bit is
changed.
The DMA request bit turns to “1” if a DMA transfer request signal occurs, and turns to “0” immediately
before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the DMA
request bit, if read by use of a program, turns out to be “0” in most cases. To examine whether the DMAC
is active, read the DMA enable bit.
The timing changes of the DMA request bit are discussed in the following section.