
Serial Communication
131
Specifications in this manual are tentative and subject to change
Rev. E
MITSUBISHI MICROCOMPUTERS
M30245 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.93. Serial I/O-related registers (5)
Bit Symbol
Function
R W
Symbol
UiSMR3 (i = 0 to 3)
Address
03A5
16, 036516, 033516, 032516
UARTi special mode register 3 (i= 0 to 3)
Note 1: Set SS function after setting CTS/RTS disable bit (bit 4 of UARTi transfer/receive control register 0)
Note 2: Only "0" may be written.
Note 3: These bits are used for SDAi (TxDi) output digital delay when using UARTi for I2 C interface.
Otherwise, set these to "000".
Note 4: When external clock is selected, delay is increased by approximately 100ns.
When reset
00
16
Bit Name
SSE
CKPH
DINC
NODC
ERR
DL0
DL1
DL2
SS port function enable
bit (Note 1)
Clock phase set bit
Serial input port set bit
Clock output select bit
Fault error flag
SDA (TxDi) digital delay
time set bit (Notes 3,4)
0 : SS function disabled
1 : SS function enabled
0 : No clock delay
1 : Clock delay
0 : Select TxDi and RxDi (master mode)
1 : Select STxDi and SRxDi (slave mode)
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
0 : No fault error
1 : Fault error (Note 2)
0 0 0 : No delay
0 0 1 : 2-cycle of 1/f(Xin)
0 1 0 : 3-cycle of 1/f(Xin)
0 1 1 : 4-cycle of 1/f(Xin)
1 0 0 : 5-cycle of 1/f(Xin)
1 0 1 : 6-cycle of 1/f(Xin)
1 1 0 : 7-cycle of 1/f(Xin)
1 1 1 : 8-cycle of 1/f(Xin)
O
b7 b6 b5
Bit Symbol
Function
R W
Symbol
UiSMR4 (i = 0 to 3)
Address
03A4
16, 036416, 033416, 032416
UARTi special mode register 4 (i= 0 to 3)
When reset
00
16
Bit Name
STAREQ
RSTAREQ
STPREQ
STSPSEL
ACKD
ACKC
SCLHI
SWC9
Start condition generate
bit (Note)
Restart condition
generate bit (Note)
Stop condition generate
bit (Note)
SCL, SDA output select
bit
ACK data bit
ACK data output enable
bit
SCL output stop enable
bit
SCL wait output bit 3
0 : Clear
1 : Start
0 : Clear
1 : Start
0 : Clear
1 : Start
0 : Ordinal block
1 : Start/stop condition generate block
0 : ACK
1 : NACK
0 : SI /O data output
1 : ACKD output
0 : Disabled
1 : Enabled
0 : SCL "L" hold disabled
1 : SCL "L" hold enabled
O
Note: These bits automatically become "0" when a start condition is generated.
b7
b0
b1
b2
b3
b4
b5
b6
b7
b0
b1
b2
b3
b4
b5
b6
to "1".