
Rev.2.00 Oct 16, 2006
page 267 of 354
REJ09B0340-0200
M30245 Group
2. Multiple Interrupts
Figure 2.15.1. Memory map of the interrupt control registers
004916
004A16
004B16
004C16
004D16
004E16
004F16
004116
004216
004316
004416
004516
004616
004716
004816
Key input interrupt control register (KUPIC)
UART2 receive/ACK interrupt control register (S2RIC)
UART1/3 Bus collision interrupt control register (S13BCNIC)
INT1 interrupt control register (INT1IC)
Timer A1 interrupt control register (TA1IC)
USB Endpoint 0 interrupt control register (EP0IC)
Timer A2 interrupt control register (TA2IC)
UART1 receive/ACK/SSI1 interrupt control register (S1RIC)
UART0/2 Bus collision interrupt control register (S02BCNIC)
UART0 receive/ACK/SSI0 interrupt control register (S0RIC)
AD conversion interrupt control register (ADIC)
DMA0 interrupt conrol register (DM0IC)
UART3 transmit/NACK interrupt control register (S3TIC)
DMA1 interrupt control register (DM1IC)
UART2 transmit/NACK interrupt control register (S2TIC)
DMA2 interrupt control register (DM2IC)
UART1 transmit/NACK/SSI1 interrupt control register (S1TIC)
DMA3 interrupt control register (DM3IC)
UART0 transmit/NACK/SSI0 interrupt control register (S0TIC)
Timer A0 interrupt control register (TA0IC)
UART3 receive/ACK interrupt control register (S3RIC)
USB suspend interrupt control register (SUSPIC)
Timer A3 interrupt control register (TA3IC)
USB resume interrupt control register (RSMIC)
Timer A4 interrupt control register (TA4IC)
USB reset interrupt control register (RSTIC)
USB SOF interrupt control register (SOFIC)
USB Vbus detect interrupt control register (VBDIC)
USB function interrupt control register (USBFIC)
INT2 interrupt control register (INT2IC)
INT0 interrupt control register (INT0IC)
005916
005A16
005B16
005C16
005D16
005E16
005F16
005116
005216
005316
005416
005516
005616
005716
005816
005016
2.15 Multiple interrupts Usage
2.15.1 Overview of the Multiple interrupts usage
The following is an overview of the multiple interrupts usage.
(1) Interrupt control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a non-maskable interrupt using the interrupt enable flag (I flag), interrupt priority
level selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or
absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level
select bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I
flag) and the IPL are located in the flag register (FLG).
Figure 2.15.1 shows the memory map of the interrupt control registers, and Figure 2.15.2 shows the
interrupt control registers.