
1-121
Under
Specifications in this manual are tentative and subject to change
Rev. G
Clock Asynchronous Serial I/O Mode
MITSUBISHI MICROCOMPUTERS
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fig. 1.93. UARTi transmit/receive mode register in UART mode
Table 1.38. Specifications of UART Mode (2)
Item
Specification
Select function
Separate CTS/RTS pins (UART0)
UART0 CTS and RTS functions each can be assigned to separate pins
Sleep mode selection (UART0, UART1)
This mode is used to transfer data to and from one of multiple slave micro-
computers
Serial data logic switch (UART2)
This function inverts logic value of transferring data. Start bit, parity bit
and stop bit are not inverted.
T
X
D, R
X
D I/O polarity switch
This function inverts
T
X
D port output and R
X
D port input. All I/O data
level is are inverted.
Symbol
UiMR(i=0,1)
Address
03A0
16
, 03A8
16
When reset
00
16
CKDIR
UARTi transmit / receive mode registers
Internal / external clock
select bit
Stop bit length select bit
STPS
PRY
PRYE
SLEP
0 : Internal clock
1 : External clock (Note)
0 : One stop bit
1 : Two stop bits
Bit name
Function
Bit symbol
W
R
b7
b6
b5
b4
b3
b2
b1
b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
Valid when bit 6 =
“
1
”
0 : Odd parity
1 : Even parity
Odd / even parity
select bit
Parity enable bit
Sleep select bit
Symbol
U2MR
Address
0378
16
When reset
00
16
CKDIR
UART2 transmit / receive mode register
Internal / external clock
select bit
Stop bit length select bit
STPS
PRY
PRYE
IOPOL
Must always be fixed to
“
0
”
Bit name
Function
Bit symbol
W
R
b7
b6
b5
b4
b3
b2
b1
b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
b2 b1 b0
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : No reverse
1 : Reverse
Valid when bit 6 =
“
1
”
0 : Odd parity
1 : Even parity
Odd / even parity
select bit
Parity enable bit
TxD, RxD I/O polarity
reverse bit (Note)
Note: Usually set to
“
0
”
.
Note: Set the corresponding port direction register to "0".