
1-150
Under
Specifications in this manual are tentative and subject to change
Rev. G
LCD Drive Control Circuit
MITSUBISHI MICROCOMPUTERS
M30222 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fig. 1.119. LCD expansion related register (2)
Voltage Multiplier
The voltage multiplier performs threefold boosting. This circuit inputs a reference voltage for boosting from LCD
power input pin V
L1
. (However, when using a 1/2 bias, supply power to the V
L1
and V
L2
through an external resistor
divider.)
To activate the voltage multiplier, choose the segment/port and duty rate, select bias control, and set up the LCD
frame frequency counter and LCDCK count source using the segment enable register and LCD mode register,
then enable the LCD output enable bit (bit 7 at address 0122
16
) and set the voltage multiplier control bit (bit 4 at
address 0120
16
) to “1” (= voltage multiplier enabled). When voltage is input to the V
L1
pin during operating the
voltage multiplier, voltage that is twice as large as V
L1
occurs at the V
L2
pin, and voltage that is three times as large
as V
L1
occurs at the V
L3
pin.
The voltage multiplier control bit (bit 4 of the address 0120
16
) controls the voltage multiplier. When using the voltage
multiplier, apply a voltage equal to or greater than 1.3 V but not exceeding 2.1 V to the V
L1
pin before enabling the
voltage multiplier control bit.
When not using the voltage multiplier, enable the LCD output enable bit and apply an appropriate voltage to the
LCD power supply input pins (V
L1
to V
L3
). When the LCD output enable bit is disabled, the V
L3
pin is connected to
V
CC
internally.
LCD expansion register
Symbol
LEXP
Address
0130
16
When reset
00
16
Bit name
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
0 : Disable
1 : Enable
0 : SOF at rising edge
1 : SOF at falling edge
0 : No action
1 : Initiate SYNC
LCKPOL
LEXPEN
LCD clock out and polarity select bit
Function
LCD Expansion enable bit
W
R
Nothing is assigned.
These bits can neither be set nor reset. When read, the value is indeterminate.
LSYNC
LCD SYNCout initiation bit
LSTATCNF0
LSTATCNF1
LSTATEN
LCD static drive pin configuration
select bits
0 0 : SEG35 to SEG24 static
0 1 : SEG35 to SEG27 static
1 0 : SEG35 to SEG32 static
1 1 : Do not use
0 : Disable
1 : Enable
LCD static drive enable bit
LCD clock divide counter
Symbol
LCDC
Address
0132
16
When reset
Indeterminate
b7
b0
Function
W
R
Values that can be set
8 bit timer
00
16
to FF
16
X