284
Serial I/O2
(d)
Set the automatic transfer interval for each 1-byte data transfer as explained below to avoid incorrect
transmit/receive of the serial data.
Not using FLD controller
Keep the interval open for 5 cycles or more of the internal system clock from the rising edge of the
last bit of 1-byte data.
Using FLD controller
a. Gradation display OFF
Keep the interval open for 17 cycles or more of the internal system clock from the rising edge of
the last bit of 1-byte data.
b. Gradation Display ON
Keep the interval open for 27 cycles or more of the internal system clock from the rising edge of
the last bit of 1-byte data.
Tables 2.6.4 and 2.6.5 show the serial I/O2 control register 3 (address 034816) setting example.
(e)
When using an external clock, the automatic transfer interval setting becomes invalid.
Serial I/O2 control register 3, SIO2CON3 (address 034816)
Internal synchronous
clock selection bits
b7 b6 b5
0 0 0 : f(XIN) / 4
0 0 1 : f(XIN) / 8
0 1 0 : f(XIN) / 16
Automatic transfer interval set bits
(b4 to b0)
0 0 0 0 0 : 2 cycles of transfer clocks
0 0 0 0 1 : 3 cycles of transfer clocks
0 0 0 1 0 : 4 cycles of transfer clocks
0 0 0 1 1 : 5 cycles of transfer clocks
0 0 1 0 0 : 6 cycles of transfer clocks
0 0 1 0 1 : 7 cycles of transfer clocks
0 0 0 0 0 : 2 cycles of transfer clocks
0 0 0 0 1 : 3 cycles of transfer clocks
0 0 0 1 0 : 4 cycles of transfer clocks
0 0 0 0 0 : 2 cycles of transfer clocks
Not using
FLDC
Usable
Gradation
display mode
OFF
Prohibited
Usable
Prohibited
Usable
Gradation
display mode
ON
Prohibited
Usable
Prohibited
Usable
Note: Do not perform the following in the automatic transfer serial I/O mode:
Transfer within the RAM area (addresses 0040016 to 005FF16) using the DMAC
Transfer within the RAM area (addresses 0040016 to 005FF16) using assembler instructions SMOVF and SMOVB.
Table 2.6.4 Serial I/O2 control register 3, SIO2CON3 (address 034816) setting example (with internal
synchronous clock)
Serial I/O2 control register 3,
SIO2CON3 (address 034816);
Automatic transfer interval set bits
Not using FLDC
Gradation display mode OFF
Gradation display mode ON
“n” cycles of transfer clocks
Transfer clock ! n cycles
≥ 5 cycles of internal system clock
Transfer clock ! n cycles
≥ 17 cycles of internal system clock
Transfer clock ! n cycles
≥ 27 cycles of internal system clock
Table 2.6.5 Serial I/O2 control register 3, SIO2CON3 (address 034816) setting example (with external
synchronous clock)