參數(shù)資料
型號: M30201M2-XXXFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP56
封裝: PLASTIC, QFP-56
文件頁數(shù): 144/158頁
文件大?。?/td> 1633K
代理商: M30201M2-XXXFP
86
Under
development
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Figure 1.79. UARTi transmit/receive mode register in UART mode
Clock asynchronous serial I/O (UART) mode
Symbol
Address
When reset
UiMR(i=0,1)
03A016, 03A816
0016
CKDIR
UARTi transmit / receive mode registers
Internal / external clock
select bit (Note)
STPS
PRY
PRYE
SLEP
0 : Internal clock
1 : External clock
Bit name
Function
Bit symbol
W
R
b7 b6
b5
b4
b3
b2
b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
b2 b1 b0
0 : One stop bit
1 : Two stop bits
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
Stop bit length select bit
Odd / even parity
select bit
Parity enable bit
Sleep select bit
Note: UART1 can use only internal clock. Must set this bit to “1”.
Table 1.29 lists the functions of the input/output pins during UART mode. Note that for a period from
when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the N-
channel open-drain is selected, this pin is in floating state.)
Table 1.29. Input/output pin functions in UART mode
Pin name
Function
Method of selection
TxDi
(P50, P40)
Serial data output
Serial data input
Programmable I/O port
Transfer clock input
RxDi
(P51, P42)
CLK0
(P52)
Internal/external clock select bit (bit 3 at address 03A016) = “0”
Internal/external clock select bit (bit 3 at address 03A016) = “1”
Port P51 and P42 direction register (bit 1 at address 03EB16, bit 2 at
address 03EA16)= “0”
(Can be used as an input port when performing transmission only)
Port P51 and P42 direction register (bit 0 at address 03EB16, bit 0 at
address 03EA16)= “1”
(Can be used as an input port when performing reception only)
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