參數(shù)資料
型號(hào)： M2V64S40TP
廠商： Mitsubishi Electric Corporation
英文描述： 64M bit Synchronous DRAM
中文描述： 6400位同步DRAM
文件頁(yè)數(shù)： 24/52頁(yè)
文件大?。?/td> 674K
代理商： M2V64S40TP
Apr. '99
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.2)
M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT)
M2V64S30BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 2097152-WORD x 8-BIT)
M2V64S40BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 1048576-WORD x 16-BIT)
64M bit Synchronous DRAM
24
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of
the same bank
. Random
column access is allowed. Write recovery time (tWR) is required from the last data to
PRE command.
Write Interrupted by Precharge (BL=4)
CLK
Command
A0-9
A10
BA0,1
DQ
Write
Yi
0
00
PRE
0
00
ACT
Xb
Xb
00
tWR
tRP
A11
Xb
Dai0
Dai1
Dai2
[ Write Interrupted by Burst Terminate ]
A burst terminate command TBST can be used to terminate a burst write operation. In this
case, the write recovery time is not required and the bank remains active (Please see the
waveforms below). The WRITE to TBST minimum interval is one CLK.
Write Interrupted by Burst Terminate(BL=4)
CLK
Command
A0-9
A10
BA
DQ
WRITE
Yi
0
0
Dai0
DQM(x4,x8)
DQMU/L(x16)
TBST
Dai1
Dai2
DQM(x4,x8)
DQMU/L(x16)
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