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參數(shù)資料
| 型號： | M2V28S20TP-7 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 128 x 64 pixel format, LED Backlight available |
| 中文描述： | 128M的同步DRAM |
| 文件頁數(shù)： | 18/52頁 |
| 文件大?。?/td> | 639K |
| 代理商： | M2V28S20TP-7 |
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M2V28S20TP-6,-7,-8
M2V28S30TP-6,-7,-7L,-8,-8L
M2V28S40TP-7,-7L,-8,-8L
Jun. '99
MITSUBISHI LSIs
SDRAM (Rev. 1.0E)
128M Synchronous DRAM
(4-BANK x 8,388,608-WORD x 4-BIT)
(4-BANK x 4,194,304-WORD x 8-BIT)
(4-BANK x 2,097,152-WORD x 16-BIT)
18
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by the ACT command with
the bank addresses (BA0,1). A row is indicated by the row addresses A0-11. The minimum activation
interval between one bank and the other bank is tRRD.
Maximum 2 ACT commands are allowed within
tRC
, although the number of banks which are active concurrently is not limited.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active,
the precharge all command (PREA, PRE + A10=H) is available to deactivate them at the same time.
After tRP from the precharge, an ACT command to the same bank can be issued.
READ
After tRCD from the bank activation, a READ command can be issued. 1st output data is
available after the /CAS Latency from the READ, followed by (BL -1) consecutive data when the
Burst Length is BL. The start address is specified by A0-A9,A11(x4), A0-9(X8), A0-8(X16) , and
the address sequence of burst data is defined by the Burst Type. A READ command may be applied
to any active bank, so the row precharge time (tRP) can be hidden behind continuous output data by
interleaving the multiple banks. When A10 is high at a READ command, the auto-precharge
(READA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited
till the internal precharge is complete. The internal precharge starts at BL after READA. (Need to
keep tRAS min.) The next ACT command can be issued after (BL + tRP) from the previous READA.
Command
Bank Activation and Precharge All (BL=4, CL=3)
CLK
A0-9
A10
BA0,1
DQ
ACT
Xa
Xa
00
READ
Y
0
00
Qa0
Qa1
Qa2
Qa3
ACT
Xb
Xb
01
PRE
tRRD
tRCD
1
ACT
Xb
Xb
01
Precharge all
tRAS
tRP
tRCmin
2 ACT command / tRCmin
A11
Xa
Xb
Xb
OPERATIONAL DESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M2V28S30TP-7 | 128 x 64 pixel format, LED Backlight available |
| M2V28S40TP-7 | 128 x 64 pixel format, LED Backlight available |
| M2V28S30ATP | 128M Synchronous DRAM |
| M2V28S30ATP-6 | 128M Synchronous DRAM |
| M2V28S30ATP-6L | 128M Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M2V28S20TP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Synchronous DRAM |
| M2V28S30ATP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Synchronous DRAM |
| M2V28S30ATP-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Synchronous DRAM |
| M2V28S30ATP-6L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Synchronous DRAM |
| M2V28S30ATP-7 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:128M Synchronous DRAM |
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