參數(shù)資料
型號: M25P40-VMN3TP
廠商: 意法半導(dǎo)體
元件分類: DRAM
英文描述: 4 Mbit Uniform Sector, Serial Flash Memory
中文描述: 4兆位統(tǒng)一部門,串行閃存
文件頁數(shù): 17/40頁
文件大?。?/td> 232K
代理商: M25P40-VMN3TP
17/40
M25P40
Table 6. Protection Modes
Note: 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
Table 2.
.
The protection features of the device are summa-
rized in
Table 6.
.
When the Status Register Write Disable (SRWD)
bit of the Status Register is 0 (its initial delivery
state), it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has
previously been set by a Write Enable (WREN) in-
struction, regardless of the whether Write Protect
(W) is driven High or Low.
When the Status Register Write Disable (SRWD)
bit of the Status Register is set to 1, two cases
need to be considered, depending on the state of
Write Protect (W):
If Write Protect (W) is driven High, it is
possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit
has previously been set by a Write Enable
(WREN) instruction.
If Write Protect (W) is driven Low, it is
not
possible to write to the Status Register
even
if
the Write Enable Latch (WEL) bit has
previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the
Status Register are rejected, and are not
accepted for execution). As a consequence,
all the data bytes in the memory area that are
software protected (SPM) by the Block Protect
(BP2, BP1, BP0) bits of the Status Register,
are also hardware protected against data
modification.
Regardless of the order of the two events, the
Hardware Protected Mode (HPM) can be entered:
by setting the Status Register Write Disable
(SRWD) bit after driving Write Protect (W) Low
or by driving Write Protect (W) Low after
setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode
(HPM) once entered is to pull Write Protect (W)
High.
If Write Protect (W) is permanently tied High, the
Hardware Protected Mode (HPM) can never be
activated, and only the Software Protected Mode
(SPM), using the Block Protect (BP2, BP1, BP0)
bits of the Status Register, can be used.
W
Signal
SRWD
Bit
Mode
Write Protection of the
Status Register
Memory Content
Protected Area
1
Unprotected Area
1
1
0
Software
Protected
(SPM)
Status Register is Writable
(if the WREN instruction
has set the WEL bit)
The values in the SRWD,
BP2, BP1 and BP0 bits
can be changed
Protected against Page
Program, Sector Erase
and Bulk Erase
Ready to accept Page
Program and Sector Erase
instructions
0
0
1
1
0
1
Hardware
Protected
(HPM)
Status Register is
Hardware write protected
The values in the SRWD,
BP2, BP1 and BP0 bits
cannot be changed
Protected against Page
Program, Sector Erase
and Bulk Erase
Ready to accept Page
Program and Sector Erase
instructions
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