5-2 Revision 13 Revision 10 (April 2012) In Table 2-2 Recommended Operating Conditions 1, VPUMP programming voltage for ope" />
參數(shù)資料
型號： M1AGLE3000V5-FGG896I
廠商： Microsemi SoC
文件頁數(shù)： 66/166頁
文件大小： 0K
描述： IC FPGA 1KB FLASH 3M 896-FBGA
標準包裝： 27
系列： IGLOOe
邏輯元件/單元數(shù)： 75264
RAM 位總計： 516096
輸入/輸出數(shù)： 620
門數(shù)： 3000000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 896-BGA
供應商設備封裝： 896-FBGA（31x31）
Datasheet Information
5-2
Revision 13
Revision 10
(April 2012)
In Table 2-2 Recommended Operating Conditions 1, VPUMP programming voltage for
operation was changed from "0 to 3.45 V" to "0 to 3.6 V" (SAR 32256). Values for
VCCPLL at 1.2–1.5 V DC core supply voltage were changed from "1.14 to 1.26 V" to
"1.14 to 1.575 V" (SAR 34701).
The tables in the "Quiescent Supply Current" section were updated with revised notes
on IDD. Table 2-8 Power Supply State per Mode is new (SARs 34745, 36949).
(example) (SAR 37105).
"TBD" for 3.3 V LVCMOS Wide Range in Table 2-28 I/O Output Buffer Maximum
as regular 3.3 V LVCMOS" (SAR 33855). Values were also added for 1.2 V LVCMOS
and 1.2 V LVCMOS Wide Range.
The formulas in the table notes for Table 2-29 I/O Weak Pull-Up/Pull-Down
Resistances were corrected (SAR 34753).
IOSH and IOSL values were added to 3.3 V LVCMOS Wide Range Table 2-40
Figure 2-48 FIFO Read and Figure 2-49 FIFO Write have been added (SAR 34844).
Values for FDDRIMAX and FDDOMAX were added to the tables in the Input DDR "Timing
Minimum pulse width High and Low values were added to the tables in the "Global Tree
Timing Characteristics" section. The maximum frequency for global clock parameter
was removed from these tables because a frequency on the global is only an indication
of what the global network can do. There are other limiters such as the SRAM, I/Os, and
PLL. SmartTime software should be used to determine the design frequency (SAR
36952).
Revision 9
(March 2012)
revised to clarify that although no existing security measures can give an absolute
guarantee, Microsemi FPGAs implement the best security available in the industry (SAR
34665).
The Y security option and Licensed DPA Logo were added to the "IGLOOe Ordering
Information" section. The trademarked Licensed DPA Logo identifies that a product is
covered by a DPA counter-measures license from Cryptography Research (SAR
34725).
The following sentence was removed from the "Advanced Architecture" section:
"In addition, extensive on-chip programming circuitry allows for rapid, single-voltage
(3.3 V) programming of IGLOOe devices via an IEEE 1532 JTAG interface" (SAR
34685).
Values for VCCPLL at 1.5 V DC core supply voltage were changed from "1.4 to 1.6 V" to
"1.425 to 1.575 V" in Table 2-2 Recommended Operating Conditions 1 (SAR 32292).
The reference to guidelines for global spines and VersaTile rows, given in the "Global
he "Spine Architecture"
section of the Global Resources chapter in the IGLOOe FPGA Fabric User's Guide
(SAR 34731).
Revision
Changes
Page
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