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參數(shù)資料
| 型號： | M12L16161A-8T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 512K x 16Bit x 2Banks Synchronous DRAM |
| 中文描述： | 為512k × 16Bit的X 2Banks同步DRAM |
| 文件頁數(shù)： | 25/27頁 |
| 文件大小： | 566K |
| 代理商： | M12L16161A-8T |
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M12L16161A
Elite Semiconductor Memory Technology Inc.
P.
25
Publication Date : J an. 2000
Revision : 1.3u
Self Refresh Entry & Exit Cycle
*Note: TO ENTER SELF REFRESH MODE
1.
CS ,RAS& CASwith CKE should be low at the same clock cycle.
2.
After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3.
The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode, minimum
t
RAS
is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4.
System clock restart and be stable before returning CKE high.
5.
CS Starts from high.
6.
Minimum t
RC
is required after CKE going high to complete self refresh exit.
7.2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst
refresh.
C L O C K
C K E
A D D R
DQ
D QM
A 1 0 / A P
S el f R e f r es h E n t r y
A u t o R ef r e s h
: D o n ' t c a r e
S el f R ef r e s h E x i t
H i - Z
H i - Z
W E
B A
C A S
R A S
C S
*N o t e 2
*No t e 1
*No t e 4
t
R C m i n
*N o t e 6
*N o t e 5
*N ot e 7
0
1
2
3
4
5
6
8
7
9
10
11
12
13
14
15
16
17
18
19
t
S S
*Note3
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| M12S16161A | 512K x 16Bit x 2Banks Synchronous DRAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M12L16161C6TAA | 制造商:ELITE 功能描述:New |
| M12L16161C6TAASQ | 制造商:MOTOROLA 功能描述:NEW |
| M12L2561616A | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L2561616A_08 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4M x 16 Bit x 4 Banks Synchronous DRAM |
| M12L2561616A_1 | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:4M x 16 Bit x 4 Banks Synchronous DRAM |
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