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參數(shù)資料
| 型號： | M12L16161A-6T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 512K x 16Bit x 2Banks Synchronous DRAM |
| 中文描述： | 為512k × 16Bit的X 2Banks同步DRAM |
| 文件頁數(shù)： | 14/27頁 |
| 文件大?。?/td> | 566K |
| 代理商： | M12L16161A-6T |
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M12L16161A
Elite Semiconductor Memory Technology Inc.
P.
14
Publication Date : J an. 2000
Revision : 1.3u
Read & Write Cycle at Same Bank @Burst Length = 4
*Note:
1.Minimum row cycle times is required to complete internal DRAM operation.
2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z(
t
SHZ
) after the clock.
3.Access time from Row active command. tcc*
(t
RCD
+CAS latency-1)+
t
SAC
4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst)
Burst can’t end in Full Page Mode.
t
R CD
t
R C
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
C L OC K
C K E
CS
RAS
C AS
ADDR
DQM
BA
C L =2
C L =3
R a
R b
C b 0
t
O H
t
S AC
t
S HZ
t
S H Z
t
R D L
R ead
(A-B ank)
Row Active
(A-Bank)
Precharge
(A-B ank)
Precha rge
(A-B ank)
Write
(A-B ank)
Row Active
(A-Bank)
*Note3
*R AC
*Note4
*Note4
: D on't care
*Note1
Q a 0
Q a 1
Q a 2
Q a 3
D b 0
D b 3
D b 1
D b 2
Q a 0
Q a 1
Q a 2
Q a 3
D b 0
D b 3
D b 1
D b 2
t
R AC
t
R D L
C a 0
A10/ AP
R a
R b
HIGH
*Note2
WE
t
OH
t
S AC
QC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M12L16161A-7BG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM |
| M12L16161A-7BIG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM |
| M12L16161A-7T | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM |
| M12L16161A-7TG | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks Synchronous DRAM |
| M12L16161A-7TG2Q | 制造商:ESMT 制造商全稱:Elite Semiconductor Memory Technology Inc. 功能描述:512K x 16Bit x 2Banks |
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