參數(shù)資料
型號(hào)： LY530ALTR
廠商： STMICROELECTRONICS
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PBGA16
封裝： 5 X 5 MM, 1.60 MM HEIGHT, LEAD FREE, LGA-16
文件頁數(shù)： 4/30頁
文件大?。?/td> 576K
代理商： LY530ALTR
Mechanical and electrical specifications
LY530AL
12/30
2.4.2
I2C - Inter IC control interface
Subject to general operating conditions for Vdd and Top.
Figure 4.
I2C slave timing diagram (4)
4.
Measurement points are done at 0.2Vdd_IO and 0.8Vdd_IO, for both ports
Table 7.
I2C slave timing values
Symbol
Parameter
I2C Standard mode(1)
I2C Fast mode (1)
Unit
Min
Max
Min
Max
f(SCL)
SCL clock frequency
0
100
0
400
KHz
tw(SCLL)
SCL clock low time
4.7
1.3
s
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
ns
th(SDA)
SDA data hold time
0(2)
3.45
0(2)
0.9
s
tr(SDA) tr(SCL)
SDA and SCL rise time
1000
20 + 0.1Cb
(3)
300
ns
tf(SDA) tf(SCL)
SDA and SCL fall time
300
20 + 0.1Cb
(3)
300
th(ST)
START condition hold time
4
0.6
s
tsu(SR)
Repeated START condition
setup time
4.7
0.6
tsu(SP)
STOP condition setup time
4
0.6
tw(SP:SR)
Bus free time between STOP
and START condition
4.7
1.3
1.
Data based on standard I2C protocol requirement, not tested in production
2.
A device must internally provide an hold time of at least 300ns for the SDA signal (referred to VIHmin of the SCL signal) to
bridge the undefined region of the falling edge of SCL
3.
Cb = total capacitance of one bus line, in pF
SDA
SCL
tf(SDA)
tsu(SP)
tw(SCLL)
tsu(SDA)
tr(SDA)
tsu(SR)
th(ST)
tw(SCLH)
th(SDA)
tr(SCL)
tf(SCL)
tw(SP:SR)
START
REPEATED
START
STOP
START
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