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參數(shù)資料
| 型號： | LY530ALTR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 模擬信號調理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PBGA16 |
| 封裝： | 5 X 5 MM, 1.60 MM HEIGHT, LEAD FREE, LGA-16 |
| 文件頁數(shù)： | 18/30頁 |
| 文件大?。?/td> | 576K |
| 代理商： | LY530ALTR |
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LY530AL
Register description
25/30
BDU: This bit is used to inhibit output registers update until both upper and lower parts are
read. In default mode (BDU=’0’) the output registers values are updated continuosly. It is
recommended to set BDU bit to ‘1’ if the reading is not faster than the output data rate.
alg: This bit permits to decide between 16 bits left justified (default value) and 10 bits right
justified representation of data coming from the device. In this last case the most significant
bits are replaced by the bit representing the sign.
BOOT bit is used to refresh the content of internal registers stored in the flash memory
block. At the device power up the content of the flash memory block is transferred to the
internal registers related to trimming functions to permit a good behavior of the device itself.
If for any reason the content of trimming registers was changed it is sufficient to use this bit
to restore correct values. When BOOT bit is set to ‘1’ the content of internal flash is copied
inside corresponding internal registers and it is used to calibrate the device. These values
are factory trimmed and they are different for every gyroscope. They permit a good behavior
of the device and normally they have not to be changed. At the end of the boot process the
BOOT bit is set again to ‘0’.
SIM bit selects the SPI Serial Interface Mode. When SIM is ‘0’ (default value) the 4-wire
interface mode is selected. The data coming from the device are sent to SDO pin. In 3-wire
interface mode output data are sent to SDA/SDI/SDO pin.
6.3
FILTER_CFG_REG (22h)
Table 21.
FILTER_CFG_REG register
HP_BW1
HP_BW0
LP_BW2
LP_BW1
LP_BW0
0 (1)
1.
0 is the default value loaded at boot. This value must not be changed.
00
Table 22.
FILTER_CFG_REG description
HP_BW(1-0)
High pass filter pole frequency selection
LP_BW(2-0)
Low pass filter pole frequency selection
Table 23.
High pass filter pole -3dB frequency selection
HP_BW[1:0]
Pole frequency [Hz]
00
1.25
01
0.31
10
0.15
11
0.08
Table 24.
Low pass filter pole -3dB frequency selection
LP_BW[2:0]
Pole frequency [Hz]
000
115
001
46.1
010
21.3
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相關代理商/技術參數(shù) |
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