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參數(shù)資料
| 型號(hào)： | LXT384BE |
| 元件分類(lèi)： | 通信、網(wǎng)絡(luò)模塊及開(kāi)發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁(yè)數(shù)： | 43/80頁(yè) |
| 文件大?。?/td> | 1112K |
| 代理商： | LXT384BE |
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Octal T1/E1/J1 Transceiver
—
LXT384
Datasheet
43
Table 23. Global Control Register, GCR (0Fh)
Bit
1
Name
Function
0
JASEL0
These bits determine the jitter attenuator position:
1
JASEL1
2
JACF
This bit determines the jitter attenuator low limit 3dB corner frequency. Refer to the
Jitter Attenuator specifications for details. See
Table 42 on page 59
.
3
FIFO64
This bit determines the jitter attenuator FIFO depth:
0 = 32 bit
1 = 64 bit
4
CODEN
This bit selects the zero suppression code for unipolar operation mode:
0 = B8ZS/HDB3 (T1/E1 respectively)
1 = AMI
5
CDIS
This bit controls enables/disables the short circuit protection feature:
0 = enabled
1 = disabled
6
RAISEN
This bit controls automatic AIS insertion in the receive path when LOS occurs:
0 = Receive AIS insertion disabled on LOS
1 = RPOS/RNEG = AIS on LOS
Note: this feature is not available in data recovery mode (MCLK=High). Disable AIS
interrupts when changing this bit value to prevent inadvertent interrupts.
7
-
Reserved.
1. On power-on reset the register is set to
“
0
”
.
Table 24. Pulse Shaping Indirect Address Register, PSIAD (10h)
Bit
1
Name
Function
0-2
LENAD 0-2
The three bit value written to these bits determine the channel to be addressed. Data
can be read from (written to) the Pulse Shaping Data Register (PSDAT).
LENAD 0-2 Channel LENAD 0-2 Channel
0h 0 4h 4
1h 1 5h 5
2h 2 6h 6
3h 3 7h 7
3 -
7
-
Reserved.
1. On power-on reset the register is set to
“
0
”
.
JASEL0
JASEL1
JA Position
1
0
Transmit Path
1
1
Receive Path
0
x
Disabled
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT384LE | Telecomm/Datacomm |
| LXT386BE | PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|BGA|160PIN|PLASTIC |
| LXT386LE | PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| LXT388LE | PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
| LXT400JE | Hermetically Sealed, 3.3V, High Speed, High CMR, Logic Gate Optocoupler |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT384LE | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Telecomm/Datacomm |
| LXT386 | 制造商:INTEL 制造商全稱(chēng):Intel Corporation 功能描述:QUAD T1/E1/J1 Transceiver |
| LXT386BE | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:PCM TRANSCEIVER|QUAD|CEPT PCM-30/E-1|CMOS|BGA|160PIN|PLASTIC |
| LXT386LE | 制造商:LEVEL1 功能描述: |
| LXT388LE | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:PCM TRANSCEIVER|DUAL|CEPT PCM-30/E-1|CMOS|QFP|100PIN|PLASTIC |
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