參數(shù)資料
型號(hào)： LXT1000
英文描述： LAN TRANSCEIVER|SINGLE|HYBRID|BGA|492PIN|PLASTIC
中文描述： 網(wǎng)絡(luò)收發(fā)器|單|混合|的BGA | 492PIN |塑料
文件頁(yè)數(shù)： 5/104頁(yè)
文件大?。?/td> 1500K
代理商： LXT1000
Datasheet
5
Gigabit Ethernet Transceiver
—
LXT1000
2.7
10 Mbps Operation..............................................................................................61
2.7.1
Transmitting/Receiving...........................................................................62
2.7.2
Polarity Correction..................................................................................62
2.7.3
Link Test.................................................................................................62
2.7.4
Link Failure.............................................................................................62
2.7.5
SQE (Heartbeat).....................................................................................62
2.7.6
Jabber ....................................................................................................63
2.7.7
Preamble Generation Mode ...................................................................63
LXT1000 Operating Requirements......................................................................63
2.8.1
Power .....................................................................................................63
2.8.2
Clock ......................................................................................................63
2.8.3
RBIAS.....................................................................................................63
2.8.4
GBIAS ....................................................................................................64
Application Information
.........................................................................................65
3.1
Design Recommendations..................................................................................65
3.1.1
Device Placement ..................................................................................65
3.1.2
Ground Plane Layout .............................................................................65
3.1.3
Power Plane Layout and Filtering ..........................................................65
3.1.3.1 Decoupling Capacitors ..............................................................66
3.1.4
RBIAS and GBIAS Requirements..........................................................66
3.1.5
Twisted-Pair Layout................................................................................66
3.1.6
MAC Interface Layout.............................................................................66
3.1.7
5V Tolerance Considerations.................................................................66
3.1.8
Master/Slave Relationship Details..........................................................67
3.1.8.1 Configuring Master/Slave in Software.......................................67
3.1.8.2 Configuring Master/Slave in Hardware......................................68
3.1.8.3 Resolution of the Master/Slave Relationship.............................68
3.2
Test Information ..................................................................................................69
3.2.1
Forced Gig Operation.............................................................................69
3.2.2
Gigabit Transmit Test Clock...................................................................69
3.2.3
Scrambler/Encoder Disable (100M) .......................................................69
3.3
Magnetics Information.........................................................................................70
3.4
Component Manufacturers..................................................................................70
3.5
Typical Application Circuitry................................................................................71
3.5.1
Typical NIC Application ..........................................................................71
Test Specifications
..................................................................................................74
4.1
1000BASE-T Timing Parameters........................................................................77
4.2
100BASE-TX Timing Parameters........................................................................79
4.3
10BASE-T Timing Parameters............................................................................81
4.4
Auto-Negotiation Timing Parameters..................................................................86
4.5
MDIO Timing Parameters....................................................................................87
4.6
QSTAT Timing Parameters.................................................................................88
2.8
3.0
4.0
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