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| 型號： | LXT1000 |
| 英文描述： | LAN TRANSCEIVER|SINGLE|HYBRID|BGA|492PIN|PLASTIC |
| 中文描述： | 網(wǎng)絡(luò)收發(fā)器|單|混合|的BGA | 492PIN |塑料 |
| 文件頁數(shù)： | 18/104頁 |
| 文件大小： | 1500K |
| 代理商： | LXT1000 |
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LXT1000
—
Gigabit Ethernet Transceiver
18
Datasheet
Table 6. LXT1000 Miscellaneous Signal Descriptions
Ball #
Symbol
Type
1
Description
C22
QSTAT
O, PU
Quick Chip Status.
Link-state monitoring. See
Section 2.3.8,
“
Quick Status
Interface
”
on page 34
.
D19
QCLK
I
Quick Clock.
Clock input used for QSTAT feature. Maximum frequency is
25 MHz. (There is no minimum.)
L5
MDDIS
I
Management Disable
. When MDDIS is High, read and write operations on
the MDIO are disabled and most hardware control balls have continuous
control over their respective functions (some balls are read only at reset or
power-up). When MDDIS is Low, the MDIO supports read and write
operations, and hardware control balls establish only the initial values of their
respective functions.
K3
MDINT
O
Management Data Interrupt
. When bit 18.1 = 1, an Active Low output
indicates status change. Interrupt is cleared by reading Register 19.
AC23
AA24,
XI
XO
I
O
Crystal Input and Output
. A 25 MHz clock must be supplied at this input,
either by placing a 25 MHz crystal across XI and XO, or by driving a 25 MHz
signal directly into XI. Refer to Functional Description on
page 20
for detailed
requirements.
AB14
RBIAS
AI
Bias Control.
A 10.7 k
, 1% resistor must be tied from this ball to ground.
D9, D11,
D12, E12,
C14, B13
GBIAS
AI
GMII Bias.
Tie these balls together, and then to the anode of a 0.1
μ
f
capacitor. Tie the cathode of the capacitor to ground.
N23
RESET
I
Reset.
This active Low input is OR
’
ed with the control register Reset bit
(0.15). The LXT1000 reset cycle is extended 258
μ
s (nominal) after Reset is
de-asserted. The transmitter is held disabled until the transmit clock
frequency is within specification.
U22
PWRDWN
I
Power Down.
When High, PWRDWN forces the LXT1000 into hardware
power down mode, de-activating all functions and interfaces. This ball is
OR
’
ed with the Power Down bit 0.11.
Pull Down (P/D)
F4
P/D
-
Note:
Pull-down.
Tie Low. Tie independently to ground or through its own
resistor.
J2
P/D
-
Pull-down.
Tie Low.
B19
P/D
-
Pull-down.
Tie Low.
D6
P/D
-
Pull-down.
Tie Low.
D4
P/D
-
Pull-down.
Tie Low.
No Connect (N/C)
L23
N/C1
-
Pull down separately.
K23
N/C2
-
No Connect.
Let ball float; do not connect to anything.
1. I/O Column Coding: I = Input, O = Output, A = Analog, PU = Pull Up (Internal)
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