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參數(shù)資料
| 型號(hào)： | LV8573M |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | LV8573A Low Voltage Real Time Clock (RTC) |
| 中文描述： | LV8573A低電壓實(shí)時(shí)時(shí)鐘（RTC） |
| 文件頁(yè)數(shù)： | 13/18頁(yè) |
| 文件大?。?/td> | 306K |
| 代理商： | LV8573M |
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Control and Status Register Address Bit Map
D7
D6
D5
D4
D3
D2
D1
D0
1. Reset by
writing
1 to bit.
Main Status Register
PS
e
X
R/W
RS
e
X
R/W
ADDRESS
e
00H
R/W
R/W
R/W
1
R/W
1
R
2
R
3
RAM
Register
Select
RAM
RAM
Alarm
Interrupt
Periodic
Interrupt
Power Fail
Interrupt
Interrupt
Status
2. Set/reset by
voltage at
PFAIL pin.
3. Reset when
all pending
interrupts
are removed.
Periodic Flag Register
PS
e
0
R/W
RS
e
0
Address
e
03H
4. Read Osc fail
Write 0 Batt-
Backed Mode
Write 1 Single
Supply Mode
R/W
4
R
5
R
5
R
5
R
5
R
5
R
5
Test
Mode
Osc. Fail/
Single Supply
1 ms
Flag
10 ms
Flag
100 ms
Flag
Seconds
Flag
10 Second
Flag
Minute
Flag
5. Reset by
positive edge
of read.
Time Save Control Register
PS
e
0
RS
e
0 Address
e
04H
Time Save
Enable
N/A
RAM
RAM
RAM
RAM
RAM
RAM
All Bits R/W
Real Time Mode Register
PS
e
0
RS
e
1
Address
e
01H
RAM
RAM
RAM
Interrupt EN
on Back-Up
Clock
Start/Stop
12/24 Hr.
Mode
Leap Year
MSB
Leap Year
LSB
All Bits R/W
Output Mode Register
PS
e
0
RS
e
1
Address
e
02H
MFO as
Crystal
RAM
RAM
RAM
RAM
RAM
RAM
RAM
All Bits R/W
Interrupt Control Register 0
PS
e
0
RS
e
1
Address
e
03H
1 ms
Interrupt
Enable
10 ms
Interrupt
Enable
100 ms
Interrupt
Enable
Seconds
Interrupt
Enable
10 Second
Interrupt
Enable
Minute
Interrupt
Enable
RAM
RAM
All Bits R/W
Interrupt Control Register 1
PS
e
0
RS
e
1
Address
e
04H
Power Fail
Interrupt
Enable
Alarm
Interrupt
Enable
DOW
Interrupt
Enable
Month
Interrupt
Enable
DOM
Interrupt
Enable
Hours
Interrupt
Enable
Minute
Interrupt
Enable
Second
Interrupt
Enable
All Bits R/W
Application Hints
Suggested Initialization Procedure for LV8573A in Bat-
tery Backed Applications that use the V
BB
Pin
1. Enter the test mode by writing a 1 to bit D7 in the Period-
ic Flag Register.
2. Write zero to the RAM/TEST mode Register located in
page 0, address HEX 1F.
3. Leave the test mode by writing a 0 to bit D7 in the Peri-
odic Flag Register. Steps 1, 2, 3 guarantee that if the
test mode had been entered during power on (due to
random pulses from the system), all test mode condi-
tions are cleared. Most important is that the OSC Fail
Disable bit is cleared. Refer to AN-589 for more informa-
tion on test mode operation.
4. Enter a software loop that does the following:
Set a 3 second(approx) software counter. The crystal
oscillator may take 1 second to start.
4.1 Write a 1 to bit D3 in the Real Time Mode Register (try
to start the clock). Under normal operation, this bit can
be set only if the oscillator is running. During the soft-
ware loop, RAM, real time counters, output configura-
tion, interrupt control and timer functions may be initial-
ized.
13
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