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參數(shù)資料
| 型號： | LV8572AN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | LV8572A Low Voltage Real Time Clock (RTC) |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 329K |
| 代理商： | LV8572AN |
Functional Description
(Continued)
TL/F/11417–11
FIGURE 6. System-Battery Switchover (Upper Left), Power Fail
and Lock-Out Circuits (Lower Right)
If chip select is low when a power failure is detected, a
safety circuit will ensure that if a read or write is held active
continuously for greater than 30
m
s after the power fail sig-
nal is asserted, the lock-out will be forced. If a lock-out delay
is enabled, the LV8572A will remain active for 480
m
s after
power fail is detected. This will enable the
m
P to perform
last minute bookkeeping before total system collapse.
When the host CPU is finished accessing the RTC it may
force the bus lock-out before 480
m
s has elapsed by reset-
ting the delay enable bit.
The battery switch over circuitry is completely independent
of the PFAIL pin. A separate circuit compares V
CC
to the
V
BB
voltage. As the main supply fails, the RTC will continue
to operate from the V
CC
pin until V
CC
falls below the V
BB
voltage. At this time, the battery supply is switched in, V
CC
is
disconnected, and the device is now in the standby mode. If
indeterminate operation of the battery switch over circuit is
to be avoided, then the voltage at the V
CC
pin must not be
allowed to equal the voltage at the V
BB
pin.
After the generation of a lock-out signal, and eventual
switch in of the battery supply, the pins of the RTC will be
configured as shown in Table II. Outputs that have a pull-up
resistor should be connected to a voltage no greater than
V
BB
.
TABLE II. Pin Isolation during a Power Failure
Pin
PFAIL
e
Logic 0
Standby Mode
V
BB
l
V
CC
CS, RD, WR
A0–A4
D0–D7
Oscillator
PFAIL
INTR, MFO
Locked Out
Locked Out
Locked Out
Not Isolated
Not Isolated
Not Isolated
Locked Out
Locked Out
Locked Out
Not Isolated
Not Isolated
Open Drain
The Interrupt Power Fail Operation bit in the Real-Time
Mode Register determine whether or not the interrupts will
continue to function after a power fail event.
As power returns to the system, the battery switch over cir-
cuit will switch back to V
CC
power as soon as it becomes
greater than the battery voltage. The chip will remain in the
locked out state as long as PFAIL
e
0. When PFAIL
e
1
11
相關PDF資料 |
PDF描述 |
|---|---|
| LV8573A | LV8573A Low Voltage Real Time Clock (RTC) |
| LV8573AM | LV8573A Low Voltage Real Time Clock (RTC) |
| LV8573AN | LV8573A Low Voltage Real Time Clock (RTC) |
| LV8573AV | LV8573A Low Voltage Real Time Clock (RTC) |
| LV8573M | LV8573A Low Voltage Real Time Clock (RTC) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LV8572AVX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
| LV8573A | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LV8573A Low Voltage Real Time Clock (RTC) |
| LV8573AM | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LV8573A Low Voltage Real Time Clock (RTC) |
| LV8573AN | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LV8573A Low Voltage Real Time Clock (RTC) |
| LV8573AV | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LV8573A Low Voltage Real Time Clock (RTC) |
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