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參數(shù)資料
| 型號(hào)： | LV8573AN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | LV8573A Low Voltage Real Time Clock (RTC) |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數(shù)： | 1/18頁 |
| 文件大小： | 306K |
| 代理商： | LV8573AN |
TL/F/11418
L
PRELIMINARY
December 1993
LV8573A Low Voltage Real Time Clock (RTC)
General Description
The LV8573A is intended for use in microprocessor based
systems where information is required for multi-tasking, data
logging or general time of day/date information. This device
is implemented in low voltage silicon gate microCMOS tech-
nology to provide low standby power in battery back-up en-
vironments. The circuit’s architecture is such that it looks
like a contiguous block of memory or I/O ports organized as
one block of 32 bytes. This includes the Control Registers,
the Clock Counters, the Alarm Compare RAM, and the Time
Save RAM.
Time and date are maintained from 1/100 of a second to
year and leap year in a BCD format, 12 or 24 hour modes.
Day of week and day of month counters are provided. Time
is controlled by an on-chip crystal oscillator requiring only
the addition of the 32.768 kHz crystal and two capacitors.
Power failure logic and control functions have been integrat-
ed on chip. This logic is used by the RTC to issue a power
fail interrupt, and lock out the
m
P interface. The time power
fails may be logged into RAM automatically when V
BB
l
V
CC
. Additionally, two supply pins are provided. When V
BB
l
V
CC
, internal circuitry will automatically switch from the
main supply to the battery supply.
The LV8573A’s interrupt structure provides three basic
types of interrupts: Periodic, Alarm/Compare, and Power
Fail. Interrupt mask and status registers enable the masking
and easy determination of each interrupt.
Features
Y
3.3V
g
10% supply
Y
Full function real time clock/calendar
D 12/24 hour mode timekeeping
D Day of week counter
D Parallel resonant oscillator
Y
Power fail features
D Internal power supply switch to external battery
D Power Supply Bus glitch protection
D Automatic log of time into RAM at power failure
Y
On-chip interrupt structure
D Periodic, alarm, and power fail interrupts
Block Diagram
TL/F/11418–1
FIGURE 1
TRI-STATE
é
is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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