參數(shù)資料
型號(hào)： LV8057GR
元件分類： 運(yùn)動(dòng)控制電子
英文描述： STEPPER MOTOR CONTROLLER, 0.6 A, QCC28
封裝： 3.50 X 3.50 MM, VCT-28
文件頁(yè)數(shù)： 6/25頁(yè)
文件大?。?/td> 258K
代理商： LV8057GR
LV8057GR
No.A1027-14/25
Step/Hold Operation Overview
Sample Timing Chart for the Step/Hold Setting
When the Step/Hold data is set to the Hold state, the state of the external clock signal (CLK) at that time is latched and
held as the internal clock signal.
At the timing with which Step/Hold is set to the Hold state for the first time in the figure below, the internal clock signal
will be held at the low level because the external clock (CLK) was at the low level. In contrast, at the timing with which
Step/Hold is set to the Hold state for the second time, the internal clock signal will be held at the high level because the
external clock (CLK) was at the high level.
When Step/Hold is set to the Clear state, the internal clock is synchronized with the external clock (CLK). The output
holds the state it was in at the point Step/Hold is set to the Hold state, and advances on the next clock signal rising edge
after Step/Hold is set to the Clear state.
As long as Step/Hold is in the Hold state, the position number does not advance even if an external clock (CLK) signal is
applied.
logic
CLK (external)
Internal CLK
Internal logic
"Step/Hold" setting signal
logic
(8)
(7)
(1)
(6)
(7)
(5)
(3)
(4)
(1)
(2)
CLK (external)
Internal clock
Step/Hold
Clear
Hold
Clear
Hold
Hold state
Held at low level
Held at high level
(Position number)
(%)
100
0
100
-100
0
(%)
I2
I3
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PDF描述
LV8105W BRUSHLESS DC MOTOR CONTROLLER, 0.02 A, PQFP48
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LV8731V STEPPER MOTOR CONTROLLER, PDSO44
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