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參數(shù)資料
| 型號： | LV8041FN |
| 元件分類： | 運動控制電子 |
| 英文描述： | STEPPER MOTOR CONTROLLER, 0.6 A, QCC52 |
| 封裝： | 7 X 7 MM, VQFN-52 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 802K |
| 代理商： | LV8041FN |
LV8041FN
No.7944-16/24
Hold Bit (D5) Operational Description
Internal logic
(External) clock
Internal clock
HOLD(D5)
logic
(External)
clock
HOLD (D5)
Channel
1 output
Channel
2 output
Internal
clock
Held at the
low level
0%
Held at the
high level
Hold state
Step/hold
(1)
Step/hold
release
Step/hold
(2)
Step/hold
release
When the HOLD bit (D5) is set to 1, the internal clock signal is held at the state of the external clock at that point.
Since the external clock is low at the timing of the step/hold (1) operation in the figure, the internal clock is then held at
the low level. Similarly, since the external clock is high at the timing of the step/hold (2) operation in the figure, the
internal clock is then held at the high level.
When the HOLD bit (D5) is set to 0, the internal clock is synchronized with the normal (external) clock.
The outputs retain their states at the time the step/hold operation was input, and after the step/hold is released, they
proceed with the timing of the next input clock rising edge.
As long as the IC is in the hold state, the position number will not be advanced even if the external clock signal is input.
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