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參數(shù)資料
| 型號(hào)： | LV5254LG |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PBGA24 |
| 封裝： | 3 X 3 MM, FLGA-24 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 136K |
| 代理商： | LV5254LG |
LV5254LG
No.A0584-5/14
Block Diagram and Application Circuit Example 1 (Internal fixed-voltage mode)
Use ceramic capacitors for the external capacitors and connect them as close as possible to the IC. We recommend
using class B devices with excellent temperature characteristics.)
Use capacitors with the same values for the charge pump capacitors C1 and C2.
We recommend a capacitance of 1
μF for C1 and C2. (See figure 4 on page 10)
SVDD and PVDD must be at the same potential. Short them together with the shortest possible line and use a ceramic
capacitor with a value of 1
μF or greater for C4 (which is inserted between this point and PGND). C4 must be mounted
as close as possible to the IC.
C6 is a phase compensation capacitor. It is required for stable regulator operation.
VREF
C1+
C1-
VOUT
C2 = 1
μF
FB
STBY
PGND
ON
OFF
C1 = 1
μF
C5 = 1
μF
OSC
PVDD
VDD
C4 = 10
μF
VREF
C3 = 0.1
μF
VS
+
S1
S2
SGND
SVDD
TEST
C6
VOUT
Charge
Pump
Clock
Driver
Output Tr
Error Amplifier
Overcurrent
Protection
Thermal
Shutdown
Discharge
C2
VDD
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