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參數(shù)資料
| 型號(hào)： | LUC4AU01 |
| 廠商： | Lineage Power |
| 英文描述： | ATM Layer UNI Manager (ALM)(ATM 層UNI管理器(ALM)) |
| 中文描述： | ATM層統(tǒng)一管理（ALM）的（自動(dòng)柜員機(jī)層統(tǒng)一管理器（簡(jiǎn)稱ALM）） |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大?。?/td> | 164K |
| 代理商： | LUC4AU01 |
4
Lucent Technologies Inc.
Preliminary Product Brief
March 1997
ATM Layer UNI Manager (ALM)
LUC4AU01
S
LUCENT TECHNOLOGIES—PROPRIETARY
Use pursuant to Company Instructions
Description
(continued)
UTOPIA MPHY Interface (UMI)
The UMI controls the transfer of ATM cells between the
ALM and multiple physical layer devices (MPHYs) con-
nected to ALM via the UTOPIA Level II MPHY inter-
face.
The chip transmits and receives ATM cells via a pair of
16-bit wide buses, using cell-level handshake flow con-
trol for up to 30 UNIs or NNIs. The UMI also checks
header errors (HEC) on the ingress cells and inserts a
locally calculated HEC into the egress cells. Cells
received with incorrect HEC are either corrected or
dropped depending on the appropriate setting in the
configuration register.
Look Up Unit (LU)
Based on the incoming VPI and VCI, the look-up unit
performs a two-level look up to fetch connection infor-
mation (from external memory) for an ingress cell. It
supports range check on VPI and VCI. The VPI and VCI
values of ingress cells are checked against maximum
values for an active connection set up. Cells with invalid
VPI or VCI values are dropped or captured depending
on the settings in the configuration registers. The look-
up unit also recognizes OA&M and ABR RM cells
received on ingress by examining the first two bytes of
the cell payload.
Policing Unit (POL)
The policing unit checks ingress cells for conformance
to their negotiated traffic contracts.
It uses the ATM Forum-compliant dual leaky-bucket
algorithm to determine if the cell should be tagged or
dropped. Policing can be enabled or disabled on a per-
VP basis, as well as globally enabled or disabled. The
policing action, tag or drop, can be programmed sepa-
rately for each individual leaky bucket on a per-connec-
tion basis.
Statistics Counters (CNT)
This block maintains per-connection 31-bit statistic
counters for the ingress and egress cells. These
counters are stored in external memory. They can be
written or read through the microprocessor interface.
The statistics feature can be globally enabled or dis-
abled. There are six counters available for each con-
nection (four for ingress, two for egress).
Microprocessor Interface (MPI)
The MPI allows an external processor to access the
ALM for configuration, maintenance, and internal and
external memory reads and writes (e.g., for call set or
tear down). It provides a 16-bit asynchronous interface
to
Intel
,
Motorola
, or generic microprocessors. It also
generates an interrupt when status bits are set.
Configuration Registers (FIG)
The configuration registers store all user-programma-
ble values. They allow the external microprocessor to
control the following, for example: to enable/disable
global statistics gathering, policing, HEC correction,
and generation of time slot synchronization signal. It
also allows configuration of base addresses for tables
in external memory for policing parameters, translation,
VC parameters, and counters. It is also used to deter-
mine the size of prepended local routing headers.
External Memory Interface (EMI)
The external memory interface is responsible for
accessing external memory (composed of synchro-
nous SRAMs). It is used for scheduling accesses and
sends control signals for ALM internal functions or
microprocessor-requested operations (e.g., call setup
or tear down, collect statistics). The ALM supports a
32-bit wide interface to synchronous SRAMs (20 ns
cycle time, nonpipelined, registered input), with a maxi-
mum depth of 512 Kwords.
Buffer Module Interface (BMI)
The BMI manages the UTOPIA II Plus ingress and
egress data buses and control signals to allow for com-
munication between the ALM and an external buffer
manager/module (e.g., the LUC4AB01 ATM Buffer
Manager, ABM, device) on the ATM layer (switch) side
of ALM. The BMI optionally captures and routes man-
agement cells to a microprocessor accessible FIFO.
The BMI inserts cell identification bits (OA&M flows,
forward and backward ABR RM, and policing outcome
as conforming/nonconforming in the local routing
header.
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