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參數(shù)資料
| 型號： | LUC4AU01 |
| 廠商： | Lineage Power |
| 英文描述： | ATM Layer UNI Manager (ALM)(ATM 層UNI管理器(ALM)) |
| 中文描述： | ATM層統(tǒng)一管理（ALM）的（自動柜員機(jī)層統(tǒng)一管理器（簡稱ALM）） |
| 文件頁數(shù)： | 2/6頁 |
| 文件大小： | 164K |
| 代理商： | LUC4AU01 |
2
Lucent Technologies Inc.
Preliminary Product Brief
March 1997
ATM Layer UNI Manager (ALM)
LUC4AU01
S
LUCENT TECHNOLOGIES—PROPRIETARY
Use pursuant to Company Instructions
Description
Figure 1 shows the architecture of an ATM switch
designed with the ATLANTA chip set. The LUC4AU01
ATM UNI Layer Manager (ALM) chip performs the ATM
layer network interface (UNI or NNI) management func-
tions for an MPHY line card and can be programmed to
work with proprietary ATM switch fabric cores.
The ALM operates in a full-duplex manner, with a max-
imum ATM cell traffic rate of 662 Mbits/s in each direc-
tion. The ingress side processes cells arriving from the
UNI; the egress side processes cells being sent to the
UNI.
5-4554r9
Figure 1. Architecture of an ATM Switch Using the ATLANTA Chip Set
ALM
LUC4AU01
MICROPROCESSOR
INTERFACE
SRAM
LINE CARD #1
#1
#1
#1
LINE CARD #N
N x N SWITCH FABRIC
#N
#N
B
R
ABM
LUC4AB01
SRAM
PHYSICAL LAYER
INTERFACE (MPHY)
ALM
LUC4AU01
SRAM
ABM
LUC4B01
SRAM
ASX
LUC4AS01
ACE
LUC4AC01
ASX
LUC4AS01
ASX
LUC4AS01
ACE
LUC4AC01
ASX
LUC4AS01
#1
#1
N x N REDUNDANT SWITCH FABRIC
#N
ASX
LUC4AS01
ACE
LUC4AC01
ASX
LUC4AS01
ASX
LUC4AS01
ACE
LUC4AC01
ASX
LUC4AS01
#1
#1
#N
INGRESS DIRECTION
EGRESS DIRECTION
#1
#N
#N
#N
#N
1
M
PHY PORTS
1
M
PHY PORTS
MICROPROCESSOR
INTERFACE
MICROPROCESSOR
INTERFACE
MICROPROCESSOR
INTERFACE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| LUC4AU01SC5DB | 制造商:LUCENT 功能描述:* |
| LUC4AU01-SC5-DB | 制造商:Agere Systems 功能描述: |
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