參數(shù)資料
型號(hào)： LTM9005CV-AA#PBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PBGA204
封裝： 22 X 15 MM, 4.32 MM HEIGHT, LEAD FREE, MO-222, LGA-204
文件頁(yè)數(shù)： 10/24頁(yè)
文件大?。?/td> 468K
代理商： LTM9005CV-AA#PBF
LTM9005
18
9005p
The DAC used to control GAIN will contribute a non-neg-
ligible amount of voltage noise. (Text to come—discuss
further and provide noise analysis.)
In some applications it may be sufficient to permanently
set the gain to a fixed level. This simplifies the circuitry as
a fixed resistor to ground can be implemented.
DIGITAL OUTPUTS
Table 3 shows the relationship between the analog input
voltage, the digital data bits, and the overflow bit.
Table 3. Output Codes vs Input Voltage, LTM9005-AA
INPUT
(SENSE = VDD)
OF
D13 – D0
(OFFSET BINARY)
D13 – D0
(2’S COMPLEMENT)
Overvoltage
Maximum
1
0
11 1111 1111 1111
11 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1110
0
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
Minimum
Undervoltage
0
1
00 0000 0000 0001
00 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0000
applicaTions inForMaTion
Figure 11. Automatic Gain Control Circuit
Minimumgainisachievedbysinkingapproximately10mA
from the GAIN pin. If the gain is to be adjusted as part of
an active control loop then the circuit in Figure 11 can be
used. See the Typical Performance Characteristics for the
transfer function.
Figure 12. Digital Output Buffer
Digital Output Modes
Figure 12 shows an equivalent circuit for a single output
buffer.EachbufferispoweredbyOVDDandOGND,isolated
fromtheADCpowerandground.TheadditionalN-channel
transistor in the output driver allows operation down to
low voltages. The internal resistor in series with the output
makes the output appear as 50Ω to external circuitry and
may eliminate the need for external damping resistors.
Aswithallhighspeed/highresolutionconvertersthedigital
output loading can affect the performance. The digital
outputs of the ADC should drive a minimal capacitive load
to avoid possible interaction between the digital outputs
and sensitive input circuitry. For full speed operation, the
capacitive load should be kept under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Data Format
Using the MODE pin, the ADC parallel digital output can
be selected for offset binary or 2’s complement format.
ConnectingMODEtoGNDor1/3VDDselectsstraightbinary
output format. Connecting MODE to 2/3VDDorVDDselects
2’scomplementoutputformat.Anexternalresistivedivider
can be used to set the 1/3VDD or 2/3VDD logic values.
Table 5 shows the logic states for the MODE pin.
LTM9005
9005 F12
OVDD
VDD
43
TYPICAL
DATA
OUTPUT
OGND
OVDD 0.5V
TO 3.6V
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
49.9
TBD
9005 F11
LTM9005
GAIN
VCC1
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