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參數(shù)資料
| 型號(hào)： | LTM4600IVPBF |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 10A High Effi ciency DC/DC レModule |
| 中文描述： | 10A條高艾菲布缺陷直流/直流レ模塊 |
| 文件頁數(shù)： | 9/24頁 |
| 文件大?。?/td> | 370K |
| 代理商： | LTM4600IVPBF |
LTM4600
9
4600fa
APPLICATIU
The typical LTM4600 application circuit is shown in Figure
17. External component selection is primarily determined
by the maximum load current and output voltage.
W
U
U
down when Q
DOWN
is on and Q
UP
is off. If the output
voltage V
O
needs to be margined up/down by ±M%, the
resistor values of R
UP
and R
DOWN
can be calculated from
the following equations:
(
)
(
100
%)
(
)
.
R
R
V
M
k
R
R
V
SET
UP
O
+
SET
UP
1
0 6
+
=
R
V
M
R
R
k
V
SET
O
SET
DOWN
(
100
( – %)
1
)
.
0 6
+
=
Input Capacitors
The LTM4600 μModule should be connected to a low
ac-impedance DC source. High frequency, low ESR input
capacitors are required to be placed adjacent to the mod-
ule. In Figure 20, the bulk input capacitor C
IN
is selected
for its ability to handle the large RMS current into the
converter. For a buck converter, the switching duty-cycle
can be estimated as:
Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:
D
V
V
O
IN
=
In the above equation,
η
% is the estimated efficiency of
the power module. C1 can be a switcher-rated electrolytic
aluminum capacitor, OS-CON capacitor or high volume
ceramic capacitors. Note the capacitor ripple current
ratings are often based on only 2000 hours of life. This
makes it advisable to properly derate the input capacitor,
or choose a capacitor rated at a higher temperature than
required. Always contact the capacitor manufacturer for
derating requirements.
In Figure 16, the input capacitors are used as high fre-
quency input decoupling capacitors. In a typical 10A
output application, 1-2 pieces of very low ESR X5R or
X7R, 10μF ceramic capacitors are recommended. This
decoupling capacitor should be placed directly adjacent
I
I
D
D
CIN RMS
(
O MAX
(
η
)
)
%
(
)
=
1
Output Voltage Programming and Margining
The PWM controller of the LTM4600 has an internal
0.6V±1% reference voltage. As shown in the block diagram,
a 100k/0.5% internal feedback resistor connects V
OUT
and
FB pins. Adding a resistor R
SET
from V
OSET
pin to SGND
pin programs the output voltage:
Table 1 shows the standard vaules of 1% R
SET
resistor
for typical output voltages:
Table 1.
R
SET
(k
Ω
)
V
O
(V)
V
V
k R
R
SET
O
SET
=
0 6
.
100
Open
100
66.5
49.9
43.2
31.6
22.1
13.7
0.6
1.2
1.5
1.8
2
2.5
3.3
5
Voltage margining is the dynamic adjustment of the output
voltage to its worst case operating range in production
testing to stress the load circuitry, verify control/protec-
tion functionality of the board and improve the system
reliability. Figure 2 shows how to implement margining
function with the LTM4600. In addition to the feedback
resistor R
SET
, several external components are added.
Turn off both transistor Q
UP
and Q
DOWN
to disable the
margining. When Q
UP
is on and Q
DOWN
is off, the output
voltage is margined up. The output voltage is margined
Figure 2.
PGND
SGND
4600 F02
LTM4600
V
OUT
V
OSET
R
SET
R
UP
Q
UP
100k
2N7002
R
DOWN
Q
DOWN
2N7002
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