參數(shù)資料
型號(hào)： LTCZQ
廠商： Linear Technology Corporation
英文描述： 16-/14-/12-Bit VOUT DACs in 3mm 】 3mm DFN
中文描述： 16/14/12 VOUT電源數(shù)模轉(zhuǎn)換器采用3mm DFN封裝】3毫米
文件頁(yè)數(shù)： 16/20頁(yè)
文件大?。?/td> 317K
代理商： LTCZQ
LTC2641/LTC2642
16
26412f
Op Amp Specifications and Bipolar DAC Accuracy
The op amp contributions to unipolar DAC error discussed
above apply equally to bipolar operation. The bipolar ap-
plication circuit gains up the DAC span, and all errors, by
a factor of 2. Since the LSB size also doubles, the errors
in LSBs are identical in unipolar and bipolar modes.
One added error in bipolar mode comes from I
B
(IN
–
),
which flows through R
FB
to generate an offset. The full
bias current offset error becomes:
V
OFFSET
= (I
B
(IN
–
) R
FB
– I
B
(IN
+
) R
OUT
2) [Volts]
So:
=
(
V
I IN
(
k I IN
– (
28
k
k
V
OFFSET
REF
)
+
)
)
.
–
12 4
33
[
]
LSB
Settling Time with Op Amp Buffer
When using an external op amp, the output settling time will
still include the single pole settling on the LTC2641/LTC2642
V
OUT
node, with time constant R
OUT
(C
OUT
+ C
L
) (see Un-
buffered V
OUT
Settling Time). C
L
will include the buffer input
capacitance and PC board interconnect capacitance.
The external buffer amplifier adds another pole to the output
response, with a time constant equal to (fbandwidth/2
π
).
For example, assume that C
L
is maintained at the same
value as above, so that the V
OUT
node time constant is
83ns = 1μs/12. The output amplifier pole will also have a
time constant of 83ns if the closed-loop bandwidth equals
(1/2
π
83ns) = 1.9MHz. The effective time constant of
two cascaded single-pole sections is approximately the
root square sum of the individual time constants, or √
2
83ns = 117ns, and 1/2 LSB settling time will be ~12
117ns = 1.4μs. This represents an ideal case, with no slew
limiting and ideal op amp phase margin. In practice, it
will take a considerably faster amplifier, as well as careful
attention to maintaining good phase margin, to approach
the unbuffered settling time of 1μs.
The output settling time for bipolar applications (Figure 3)
will be somewhat increased due to the feedback resistor
network R
FB
and R
INV
(each 28k nominal). The parasitic
capacitance, C
P
, on the op amp (–) input node will introduce
a feedback loop pole with a time constant of (C
P
28k/2).
A small feedback capacitor, C1, should be included, to
introduce a zero that will partially cancel this pole. C1
should nominally be <C
P
, typically in the range of 5pF
to 10pF. This will restore the phase margin and improve
coarse settling time, but a pole-zero doublet will unavoid-
ably leave a slower settling tail, with a time constant of
roughly (C
P
+ C1) 28k/2, which will limit 16-bit settling
time to be greater than 2μs.
Reference and GND Input
The LTC2641/LTC2642 operates with external voltage refer-
ences from 2V to V
DD
, and linearity, offset and gain errors
are virtually unchanged vs V
REF
. Full 16-bit performance
can be maintained if appropriate guidelines are followed
when selecting and applying the reference. The LTC2641/
LTC2642’s very low gain error tempco of 0.1ppm/°C, typi-
cal, corresponds to less than 0.5LSB variation over the
–40°C to 85°C temperature range. In practice, this means
that the overall gain error tempco will be determined almost
entirely by the external reference tempco.
The DAC voltage-switching mode “inverted” resistor ladder
architecture used in the LTC2641/LTC2642 exhibits a refer-
ence input resistance (R
REF
) that is code dependent (see
the Typical Performance curves I
REF
vs Input Code).
In unipolar mode, the minimum R
REF
is 14.8k (at code
871Chex, 34,588 decimal) and the the maximum R
REF
is
300k at code 0000hex (zero scale). The maximum change
in I
REF
for a 2.5V reference is 160μA. Since the maximum
occurs near midscale, the INL error is about one half of the
change on V
REF
, so maintaining an INL error of <0.1LSB
requires a reference load regulation of (1.53ppm 2/160μA)
= 19 [ppm/mA]. This implies a reference output impedance
of 48m
Ω
, including series wiring resistance.
To prevent output glitches from occuring when resistor
ladder branches switch from GND to V
REF
, the reference
input must maintain low impedance at higher frequencies.
A 0.1μF ceramic capacitor with short leads between REF
and GND provides high frequency bypassing. A surface
mount ceramic chip capacitor is preferred because it has
the lowest inductance. An additional 1μF between REF
and GND provides low frequency bypassing. The circuit
will benefit from even higher bypass capacitance, as long
as the external reference remains stable with the added
capacative loading.
APPLICATIONS INFORMATION
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